Lecture 6. CMOS Device (cont) ECE 407/507 Devices © Digital Integrated Circuits
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Transcript Lecture 6. CMOS Device (cont) ECE 407/507 Devices © Digital Integrated Circuits
Lecture 6. CMOS Device (cont)
ECE 407/507
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Notice
Reading Assignment
: chapter 1,
chapter 3 (finish reading)
Both hw1 and lab1 are on the website
hw1 due in one week (next Thurs.)
Lab1 due in two week (the Thurs. after
next )
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The Transistor as a Switch
VGS V T
Ron
S
ID
V GS = VD D
D
Rmid
R0
V DS
VDD/2
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VDD
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The Transistor as a Switch
7
x 10
5
6
Req (Ohm)
5
4
3
2
1
0
0.5
1
1.5
V
DD
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2.5
(V)
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The Transistor as a Switch
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C GCB_1
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C GCS
C GCD
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The Sub-Micron MOS Transistor
Threshold
Variations
Subthreshold Conduction
Parasitic Resistances
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Threshold Variations
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS )
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Low VDS threshold
VDS
Drain-induced barrier lowering
(for low L)
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Sub-Threshold Conduction
The Slope Factor
-2
10
Linear
-4
I D ~ I 0e
10
-6
Quadratic
, n 1
CD
Cox
S is DVGS for ID2/ID1 =10
ID (A)
10
qVGS
nkT
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
1
1.5
2
2.5
Typical values for S:
60 .. 100 mV/decade
VGS (V)
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Sub-Threshold ID vs VGS
I D I 0e
qVGS
nkT
qV
DS
1 e kT
VDS from 0 to 0.5V
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Sub-Threshold ID vs VDS
I D I 0e
qVGS
nkT
qV
DS
1 e kT
1 VDS
VGS from 0 to 0.3V
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Summary of MOSFET Operating
Regions
Strong
Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak
Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS dependence
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Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
D
S
RS
W
VGS,eff
RD
Drain
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Future Perspectives
25 nm FINFET MOS transistor
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New Tech: Silicon On Insulator (SOI)
Silicon
wafers are highly perfect :
critically important for achieving high
device yield.
But a more radical change may be
needed in the material structure,
processing method, or device design in
order to enhance the circuit
performance.
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Why use SOI
Extend
the life of traditional silicon
technology
Boost speed
Reduce power consumption
Solve some scaling difficulties
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Transistor crosssection
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SOI material structure
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Benefits of SOI -performance
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Benefits of SOI -- power
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Benefits of SOI – timing
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SiGe: Silicon Germanium
Used
to be inefficient in chip production
Extremely high frequencies: 60Ghz
Very little power usage
70% faster, 35% less power
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Why SiGe
The layer of latticed silicon and germanium added to the
chips silicon layer increases the distance between
silicon atoms
Less force between atoms, easy for electrons to pass
by with less resistance
IBM suggests combining SiGe and SOI
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Thermal problem with SiGe
The diagram above shows the effect of localized self-heating in the emitters
(30C for 40mv)
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