Transcript Combinational Logic Design

Combinational
Logic Design




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Combinational Circuits
Design Topics
Analysis Procedure
Design Procedure
Common Building Blocks
Hardware Design Languages
Read MK 87-124, 141-161, 201-229
4 Bit ALU Design Elements
Negate
A
B
4 Bit Adder
Negate
Negate
4 Bit Adder
4 Bit Adder
D
S
if S=0 then D=B-A
if S=1 then D=A-B
if S=2 then D=A+B
if S=3 then D=-A
3.‹#› - Jon Turner - 5/24/2016
Quad 4:1 Multiplexor
Combinational Circuits
A
Combinational Circuit
B
A
Non-combinational Circuit
B
 In
combinational circuits, there is no way for a signal to
flow from a gate output to one of its inputs.
» so, outputs depend only on current input values (not past)
» non-combinational circuits use feedback to implement storage
 Combinational
circuits are essential building blocks.
 Each output of a combinational circuit is a function of
the input values.
» each output can be specified by a truth table or Boolean exp.
» analysis: circuit  specification
» synthesis: specification  circuit
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Hierarchical Design
 Complex
systems are designed by assembling simpler
parts in a systematic and (usually) hierarchical way.
» complex function at top of hierarchy, simple gates at bottom
» design process can be top-down or bottom-up
 Key
concept is composition of simpler circuit blocks to
produce more complex blocks.
top level spec
X0
X1
X2 9 input
X3
Z0
X4 odd
X5
X6function
X7
X8
X03 input Z0
X1
X2 odd
X03 input Z0
X1
X2 odd
X03 input Z0
X1
X2 odd
X03 input Z0
X1
X2 odd
Z0=odd(X0,…,X8)
odd(X0,…,X8)=odd(odd(X0,X1,X2),
odd(X3,X4,X5),odd(X6,X7,X8))
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odd(X0,X1,X2)
=odd(X0,odd(X1,X2))
odd(X0,X1)=
nand(nand(X0,nand(X0,X1)),
nand(X1,nand(X0,X1)))
Design Concepts
 Hierarchical
design is essential for managing
complexity & allows us to understand larger circuits.
 Design re-use is a key tool for reducing design effort.
» apply common building blocks (functional blocks) to construct
larger systems
» large designs may contain many instances of a given block
» generic design elements implement common functions but may
differ based on parameter values
– e.g. an odd function block, with number of inputs as a parameter
 Top-down
design, goes from high level specification to
simpler components using iterative refinement.
 In bottom-up design, we identify & construct common
elements that can be re-used multiple times.
3.‹#› - Jon Turner - 5/24/2016
Analyzing Combinational Circuits
Purpose of analysis is to determine what a circuit does.
 Procedure

1. verify that circuit is combinational
2. label all inputs, outputs and internal nets
3. write logic equations for internal nets in terms of inputs
4. write logic equations for outputs in terms of inputs
and simplify
T1=BC T2=AB
A
T3
T =A+T =A+BC
B
C
D
3
T1
F1
T2
T4
F2
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1
T4=T2D=AB D
F1=T3+T4
=A+BC+BD +BD
F2=T2+D=AB+D
Derivation of Truth Tables
Can derive truth tables directly from circuit.
 Procedure

1. For n input circuit, truth table has 2n rows, one for each
binary number from 0 to 2n-1.
2. Label internal nets and place columns in truth table for
ABCD T1 T2 T3 T4 F1
internal nets and outputs.
0000
0 0 0 0 0
3. Fill in columns for internal nets
0001
0 0 0 1 1
0010
1 0 1 0 1
and outputs.
0011
1 0 1 1 1
0100
0 1 0 1 1
A
T3
0101
0 1 0 0 0
B
C
T1
D
F1
T2
T4
F2
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0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
F2
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
Designing Combinational Circuits
 Procedure
1. Determine number of inputs and outputs and assign a
symbol to each.
2. Derive truth table for each output.
3. Obtain Boolean expressions for each output.
4. Create an appropriate logic diagram.
5. Verify correctness by analysis and/or simulation.
» Example: design circuit with 3 inputs, 1 output; the output
should be 1 when the binary value of the inputs is <3.
XYZ
000
001
010
011
100
101
110
111
F
1
1
1
0
0
0
0
0
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YZ
00 01 11 10
X
0 1 1 0 1
1 0 0 0 0
F =X Y +X Z 
X
Y
Z
F
BCD to Excess 3 Code Converter

Excess-3 code for a decimal digit is the binary value
for the decimal number plus 3. input output CD
A
B
C
D
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W
X
Y
Z
ABCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
WXYZ
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
CD
00 01 11 10
AB
00 0 1 1 1
01 1 0 0 0
11 x x x x
10 0 1 x x
AB
00
01
11
10
00 01 11 10
0
0
x
1
0
1
x
1
0
1
x
x
0
1
x
x
W=A+BC +BD
CD
00 01 11 10
AB
00 1 0 1 0
01 1 0 1 0
11 x x x x
10 1 0 x x
X=B C +B D +BC D Y=CD +C D
Decoders
binary-to-unary decoder converts a binary input
value with n bits to one of 2n possible output values.
A0
A1
A2
A2A1A0
D0
D1
D2
D3
D4
D5
D6
D7
000
001
010
011
100
101
110
111
D7..D0
D0
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
D1
D2
D3
D4
D5
A0
A1
E
24
Decoder
Alternative
Implementation
D4
D5
D6
D7
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A0
A1
E
24
Decoder
A0
A1
A2
38 Decoder
A
D0
D1
D2
D3
D6
D7
A2
A1
A0
Decoder Schematic & Simulation
3.‹#› - Jon Turner - 5/24/2016
Encoders
A
unary-to-binary encoder converts one of 2n input
values to an encoded binary value.
D3D2D1D0 A1A0
0001
00
0010
01
0100
10
1000
11
A1=D2+D3
A0=D1+D3
A
priority encoder converts the first of 2n input values
that are 1 to the corresponding encoded binary value.
D3D2D1D0 A1A0V
0000
xx0
0001
001
001x
011
01xx
101
1xxx
111
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A1=D3+D2
A0=D 3+D2D1
V= D3+D2+D1+D0 -- valid output
Multiplexers
A
multiplexer (a.k.a. data
selector) has n control
inputs, 2n data inputs & a
single data output
» control input value
connects one data input to
output
» circuit similar to decoder
» optional enable input
allows construction of
larger muxes
–implement with AND at
output
» alternative implementation
uses transmission gates
3.‹#› - Jon Turner - 5/24/2016
D0
D1
D2
D3
Y
D4
D5
D6
D7
S2
S1
S0
Demultiplexers
A
demultiplexer has n control
inputs, 2n data outputs & a
single data input
D0
» control input value connects
data input to one of the outputs
D2
 Mux
& demux can be used to
transmit several low speed
signals on a single wire.
D0
D1
D2
D3
D1
D3
X
D4
D5
D6
D0
D1
D2
D3
S1 S 0
D7
S1 S0
S2
3.‹#› - Jon Turner - 5/24/2016
S1
S0
Choosing the Best Circuit
 Often
there are many alternative circuits we can use.
» trade-off between circuit cost and performance
 The
complexity of a circuit is the number of elementary
components needed to implement it.
» often, we count simple gates (or “gate equivalents”)
» example
– 8 bit decoder on page 3.10 requires 19 simple gates
– an n bit decoder using the same design requires n(log2n -1) + log2n
simple gates
 The
worst-case delay of a circuit is the maximum time
required for an input signal change to affect an output.
» estimate by looking for longest input-to-output path (most
simple gates) and counting one “unit” per gate in path
» can estimate more precisely if gate delays are given
3.‹#› - Jon Turner - 5/24/2016
Increment Circuit and Half Adders
A0
A1
A2
A3
increment circuit with n
inputs and n+1 outputs
computes binary value that is
one larger than its input.
 It can be implemented using n linked
half-adder circuits.
increment
 An
S0
S1
S2
S3
S4
» to obtain a selectable incrementer replace the
constant 1 input with a control input
» time for increment grows
Cin
with number of bits
Ai
S0
A1
S1
A2
S2
A3
S3
Si
Cout
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A0
1
S4
Addition Circuit and Full Adders
Addition circuit with 2n inputs &
A
n+1 outputs computes the
B
binary sum of two input values. A
B
 It can be implemented using
A
B
n linked full-adder circuits.
A
 A full-adder can be built from B
2 half-adders.
0

S0 A0
0
0
2
add
2
3
Cin

Cin
S
A
B
Cout
FA
S0
S2 A1
B1
FA
S1
A2
S4 B2
FA
S2
A3
B3
FA
S3
S3
3
A
B
FA
S1
1
1
B0
S=ABCin
Cout=AB+BC +ACin
This addition circuit is called a ripple carry adder
» takes time proportional to n to add two n bit numbers
3.‹#› - Jon Turner - 5/24/2016
S4
Simulation of Adder Circuit
Functional Simulation (no gate delays)
Timing Simulation (post place & route)
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Binary Multiplication
 Binary
multiplication is done
much like decimal
multiplication.
1101
1010
0000
1101
0000
1101
10000010
Y0 .X3 .X2.X1 X0
Y1
Addend
multiplicand
multiplier
partial products
.X3 .X2.X1 X0
Adder
C
Y2
 Requires
Sum
.X3 .X2.X1 X0
Addend
product
Augend
Adder
Augend
C
Sum
X3 X2 X1 X0
1 bit multipliers
.
. .
Y3
(AND gates) and addition
Addend
Augend
circuits.
Adder
 Can speedup by rearranging so
C Sum
additions occur in parallel.
P7P6P5P4P3P2P1P0
3.‹#› - Jon Turner - 5/24/2016
Incrementer with Carry Look-ahead
 Can
inc
speed up incrementer using carry lookahead.
 Compute carry out of each position directly
X0
from inputs.
S0
» redundant AND operations, but faster
 Speed
comparison
» assumptions: 2 input gate has 1 ns delay,
3 or 4 input gate has 2 ns delay,
5 to 8 input gate has 3 ns delay,
...
» 64 bit ripple carry incrementer needs 64 ns in
worst-case
» 64 bit carry-lookahead incrementer needs 7 ns in
worst-case
 So,
what’s the catch?
» carry lookahead uses 2000 “simple gate equivalents”
» inputs must drive many gates
3.‹#› - Jon Turner - 5/24/2016
X1
S1
X2
S2
X3
S3
S4
More Scalable Carry Lookahead
EN=c0
x0
x1
x2
x3
x4
x5
x6
c1= ENx0
x0x 1
ENx0x1
x1x2
ENx0x1x2
x2x3
x0x1x2x3
x3x 4
x4x 5
x2x3x4x5
x5x6
x3x4x5x6
x6x7
x4x5x6x7
x7
 64
x1x 2x3x4
c2= ENx0x1
c3= ENx0x1x2
c4= ENx0x1x2x3
c5= ENx0x1x2x3x4
c6= ENx0x1x2x3x4x5
c7= ENx0x1x2x3x4x5x6
c8= EN x0x1x2x3
x4x5x6x7
bit version has 7 ns delay, about 380 gates for carry, fanout=6.
3.‹#› - Jon Turner - 5/24/2016
Carry Lookahead Adder
 Ripple
carry adder is too slow for fast addition of large
values (typical computer uses 32 or 64 bit arithmetic).
 To get a faster circuit, replace long carry chain with a
“shorter” circuit. First separate carry logic in FA.
X
Y
S
partial
full adder
Cin
Cout
generate
propagate
» So high order carries can be
generated with low delay, at
the cost of more gates.
3.‹#› - Jon Turner - 5/24/2016
Let Gi be generate signal for bit
i, Pi be propagate signal and Ci
be carry into bit i.
C2=G1+C1P1=G1+G0P1+C0P0P1
and
C3=G2+C2P2
=G2+(G1+G0P1+C0P0P1)P2
=G2+G1P2+G0P1P2+C0P0P1P2
and so forth.
Simulation of Carry Lookahead Adder
C0
C1
C2
C3
Functional Simulation (0 gate delays)
C4
Unit Delay Simulation (1 ns delay per gate)
3.‹#› - Jon Turner - 5/24/2016
More Scalable Lookahead Adder
A more scalable lookahead adder can be obtained by
writing the logic equations differently.
 Let G(i,j) be true if a carry is generated from within the
bits i-j+1 up to i: G(i,j)=Gi + Gi-1Pi +  + Gi-j+1Pi-j+2Pi
 Let P(i,j)=PiPi-j+1.
 Now, we can also write,
G(i,1)=Gi
P(i,1)=Pi
G(i,2)=G(i,1)+G(i-1,1)P(i,1) P(i,2)=P(i,1)P(i-1,1)
G(i,4)=G(i,2)+G(i-2,2)P(i,2) P(i,4)=P(i,2)P(i-2,2)
G(i,8)=G(i,4)+G(i-4,4)P(i,4) P(i,8)=P(i,4)P(i-4,4)
 These equations lead directly to the design on the
following page.

3.‹#› - Jon Turner - 5/24/2016
Lookahead Adder Schematic
Up to 2+2log2n
gate delays.
About 3n+3nlog2n gates.
P(i-j,j)
Partial full
adder
P(i,j)
P(i,2j)
G(i-j,j)
G(i,j)
3.‹#› - Jon Turner - 5/24/2016
G(i,2j)
Linear Circuit Pattern
 Ripple-carry
increment and addition circuits are
examples of a common linear circuit pattern.
» copies of a common “block” with one or more signals
between adjacent blocks
...

Other circuits with similar pattern.
» 2s-complementer, maximum, comparison, count-ones, . . .


Propagation delay for such circuits typically grows in
proportion to number of blocks.
Look-ahead versions can have propagation delays
that grow with logarithm of number of blocks.
3.‹#› - Jon Turner - 5/24/2016
Modular and Signed Arithmetic
2
3
4 0100
5
6
0011+0110
=1001
1111+0011=0010
0000
 Associating
3.‹#› - Jon Turner - 5/24/2016
9 8 7
-2
-3
1100 -4
-5
-6
-1 0 1
-7 -8 7
1000
certain bit patterns
with negative values yields
signed arithmetic.
 Negate a given value by flipping
all bits and adding 1.
14
13
1100 12
11
10
15 0 1
1000
» to add A+B, start at position for A
and then count clockwise B positions
» standard addition algorithm does
exactly this.
0000
overflows are discarded, binary
adders actually implement
modulo arithmetic in which values
wrap around circularly.
1111+0011=0010
 If
2
6
3
4 0100
5
2’s Complement and Subtraction
 In
2’s complement arithmetic with n bits:
» the first bit represents the sign (0 for positive, 1 for negative)
» for positive numbers, the remaining n-1 bits give the
magnitude in standard binary notation
» to convert a positive number to corresponding negative
number, flip all bits and add 1 (00111100+1=1101)
» to convert a negative number to corresponding positive
number, flip all bits and add 1 (11010010+1=0011)
 To
subtract, take complement and add.
» 410-710 = 0100-0111 = 0100+(-0111) = 0100+1001 = 1101 = -310
 2’s
complement is most popular method for
representing negative numbers.
» requires no special subtraction circuit, just addition and
complement
3.‹#› - Jon Turner - 5/24/2016
Adder-Subtracter
 When
sub=0, result is
A+B.
 When sub=1
» bit flipper complements
all bits of B
» adder sums and adds 1
A-B = A + (-B)
= A + (not(B) + 1)
= A + not(B) + 1
 Takes
just slightly more
time than “plain” adder.
3.‹#› - Jon Turner - 5/24/2016
A3 A2 A1 A0 B3 B2 B1 B0
bit
flipper
sub
Cout
Adder
R3 R2 R1 R0
Cin
Alternative Negative Number Formats
1’s complement arithmetic, negate a value
by flipping bits (do not also add 1).
0000
 In
-1
-2
1100 -3
-4
-5
-0 0 1
2
1000
» gives two different representations for zero
6
-6 -7 7
» when adding two values, if carry out of most
significant digit, increment to obtain final sum
» comparable to 2’s complement but not quite as simple
3
4 0100
5
sign-magnitude arithmetic, left-most bit is sign and
remaining bits give magnitude.
3.‹#› - Jon Turner - 5/24/2016
-6
-5
1100 -4
-3
-2
-7 0 1
-1 -0 7
1000
» most obvious representation for people
» does not allow negative numbers to be
directly added
» requires separate subtraction hardware
0000
 In
2
6
3
4 0100
5
Computer-Aided Design
 CAD
tools are essential to the design of complex parts.
 Logic design
» schematic capture - interactive creation of logic diagrams
» hardware description languages - textual representation of
circuit function
 Design
verification
» logic simulation to check circuit behavior experimentally
» formal verification tools - automated correctness proofs and
assertion checking
» timing analysis and simulation
 Implementation
» logic synthesis - convert high level spec. to low level gates
» circuit layout - placement of components, routing of wires
» details - clock distribution, power, pads, testing
3.‹#› - Jon Turner - 5/24/2016
Hardware Description Languages
 HDLs
allow designers to work at a higher level of
abstraction than logic gates.
 As with programming languages, HDL descriptions
are compiled into a lower level representation.
» low level form can be simulated for logical correctness
» and, can be converted to a circuit specification using a library
of primitive components and timing/area constraints
 But
don’t confuse hardware design with software.
» HDL descriptions must reduce to physical hardware that can
be fit in the physical space available and meets timing specs.
» hardware designs are inherently parallel with many things
going on at once
» on the other hand, software can be used to implement much
more complex functions than hardware alone.
3.‹#› - Jon Turner - 5/24/2016
Read Sections 1,2 of VHDL Tutorial
VHDL Specification of Half Adder
library provides
commonly used types
and functions
Port declaration defines inputs
and outputs. STD_LOGIC type
used for signals.
CAD software
simulates circuit
operation.
3.‹#› - Jon Turner - 5/24/2016
May have different
implementations for a
given module.
Signal assignments
occur simultaneously.
xor, and are builtin operators
VHDL Specification of Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Compact port
entity fullAdd is
declarations
Port (
a, b, Ci : in std_logic;
S, Co : out std_logic; );
end fullAdd;
Complex logic
architecture a1 of fullAdd is
expressions.
begin
S <= a xor b xor Ci;
Co <= (a and b) or (a and Ci) or (b and Ci);
end a1
3.‹#› - Jon Turner - 5/24/2016
What Does VHDL Spec Mean?
 VHDL
specifies a circuit, not sequential execution. So,
architecture arch of fulladd is begin
s <= (a xor b) xor Ci;
Co <= (a and b) or (a and Ci) or (b and Ci);
end arch;
means
s
Co
a b Ci
 So,
what does this mean?
architecture foo of bar is begin
a <= ‘1’; b <= a; a <= ‘0’;
end bar;
3.‹#› - Jon Turner - 5/24/2016
Signal Assignments for Vectors
 Example:
entity foo is
port(a: in std_logic;
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(3 downto 0));
end foo;
architecture bar of foo is begin
c <= a & (b(0) and a) & b(2 downto 1);
end bar;
defines circuit
a
b(2)
b(1)
b(0)
c(3)
c(2)
c(1)
c(0)
3.‹#› - Jon Turner - 5/24/2016
Conditional Signal Assignment
 Example:
c <=
means
"0010" when a /= b else
"1101" when a = '1' else
"0100";
a
b
4
"0010" /
4
"1101" /
4
/ c
4
"0100" /

general form
x <=
v1 when f1(a1,b1,...) else
v2 when f2(a2,b2,...) else
v3 when f3(a3,b3,...) else
... else
vN
3.‹#› - Jon Turner - 5/24/2016

x <=
(f1(a1,b1,...) and v1) or
(not f1(a1,b1,...) and
f2(a2,b2,...) and v2) or
(not f1(a1,b1,...) and
not f2(a2,b2,...) and
f3(a3,b3,...) and v3) or
...
Selected Signal Assignment
 Example:
with x select
c <= "0010" when "00" ,
"1101" when "01" | "10" ,
“1100" when others;
means
"0010"
"1101"
"1100"
0
1
2
3
4
/
c
x
 Resulting
circuit is more compact and faster than circuit
produced by conditional assignment.
3.‹#› - Jon Turner - 5/24/2016
Important Characteristics of VHDL
 VHDL
developed for circuit modelling & simulation.
» allows specification of hardware behavior independent of implementation
» synthesis tools developed later
» not all VHDL specifications can be synthesized
 Signals
correspond to wires in circuit.
» language also supports variables - useful in behavioral models, testbenches
» best to avoid variables in synthesizable models – (except loop variables)
 Signal
assignments define logic circuits.
 Strong
typing in VHDL.
» signals on left side of assignment change as signals on right side change
(exceptions to be discussed later)
» not like sequential program execution
» signal types in expressions must match exactly
– no automatic type conversions
» bit and integer are only built-in types
» extensive support for user-defined types, such as std_logic
» std_logic defines 9 values, including 0, 1 and undefined
3.‹#› - Jon Turner - 5/24/2016
Processes and if-then-else
 Example:
process block enables use of
complex statement types
entity foo is port(
a, b: in std_logic;
c, d: out std_logic_vector(3 downto 0));
end foo;
sensitivity list must
architecture foo of bar is begin include all “input”
process (a, b) begin
signals to process
if a /= b then
c <= "0010"; d <= "1100";
elsif a = '1' then
c <= "1101"; d <= a & b & "01";
else
c <= "0100"; d <= "10" & b & a;
end if;
note that c,d defined
end process;
under all possible input
end foo;
conditions - REQUIRED
3.‹#› - Jon Turner - 5/24/2016
Avoiding Unintended Storage


If value of a signal is not specified for some condition, it means
that signal is unchanged.
Example
process(a,b) begin
if a = '1' then
x <= '0';
elsif b = '1' then
x <= '1';
end if; -- x retains value when a=b=0
end process;
Storage elements are required to implement circuit with the
specified behavior.
– if one accidentally omits a condition for a signal, unintended storage
elements are synthesized.

Easy way to avoid unintended storage is to start process with
assignment of default values to all signals assigned a value inside
the process.
3.‹#› - Jon Turner - 5/24/2016
Default Values
 Example:
entity foo is port(
a, b: in std_logic;
c, d: out std_logic_vector(3 downto 0));
end foo;
initial assignments
architecture foo of bar is begin
define “default”
process (a, b) begin
values for c and d
c <= "0100"; d <= "10" & b & a;
if a /= b then
c <= "0010"; d <= "1100";
elsif a = '1' then
c <= "1101"; d <= a & b & "01";
end if;
end process;
What values are assigned
end foo;
to c, d if we rearrange so
if-then-else comes first?
3.‹#› - Jon Turner - 5/24/2016
For-loops
entity adder8 is
Port ( Cin : in std_logic;
A, B : in std_logic_vector(7 downto 0);
S : out std_logic_vector(7 downto 0);
Cout : out std_logic);
end adder8;
architecture arch1 of adder8 is
For-loop defines multiple identical (or
signal C: std_logic_vector(8 downto 0); similar) sub-circuits.
begin
Loop does not imply sequential
process(A,B,C,Cin) begin
ordering of signal assignments.
C(0) <= Cin; Cout <= C(8);
for i in 0 to 7 loop
S(i) <= A(i) xor B(i) xor C(i);
C(i+1) <= (A(i) and B(i)) or (A(i) and C(i))
or (B(i) and C(i));
end loop;
end process;
end arch1;
Note separate carry signal for each
stage – cannot re-assign values to one
signal as in sequential programs.
3.‹#› - Jon Turner - 5/24/2016
Case Statement
 Case
statement provides convenient way to express
alternatives that depend only on value of a single signal
architecture a1 of foo is
begin
process(c,d,e) begin
b <= '1';
-- provide default value for b
case e is
when "00"
=> a <= c; b <= d;
when "01"
=> a <= d; b <= c;
when "10"
=> a <= c xor d;
when others => a <= '0';
others alternative is required
end case;
even when all “logical
end process;
alternatives” are specified
end a1;
 Creates
more efficient circuits than equivalent
if-then-else.
3.‹#› - Jon Turner - 5/24/2016
VHDL Spec. for Simple Arithmetic Unit
entity alu is
Port ( a, b : in std_logic_vector(3 downto 0);
c : in std_logic_vector(2 downto 0);
x : out std_logic_vector(3 downto 0);
v : out std_logic);
end alu;
architecture a1 of alu is
signal result: std_logic_vector(4 downto 0);
signal ax, bx: std_logic_vector(4 downto 0);
begin
ax <= '0' & a; bx <= '0' & b;
result <=
ax
when c = "000" else
bx
when c = "001" else
(not ax)+1
when c = "010" else
(not bx)+1
when c = "011" else
ax+bx
when c = "100" else
ax+bx
when c = "101" else
ax-bx
when c = "110" else
bx-ax;
x <= result(3 downto 0);
v <= '1‘ when (c = "010" and a = "1000")
or (c = "011" and b = "1000")
or (c = "100" and result(4) = '1')
or (c = "101" and a(3) =b(3) and a(3) /= result(3))
or (c = "110" and a(3)/=b(3) and a(3) /= result(3))
or (c = "111" and a(3)/=b(3) and b(3) /= result(3))
else '0';
end a1;
c=0 means x=a, c=1 means x=b,
c=2 means x= -a, c=3 means x=-b,
c=4 means x=a+b (unsigned),
c=5 means x=a+b (signed),
c=6 means x=a-b,
c=7 means x=b-a
3.‹#› - Jon Turner - 5/24/2016
v bit signals
arithmetic error
VHDL Spec. for Simple Arithmetic Unit
entity alu is
Port ( a, b : in std_logic_vector(wSiz-1 downto 0);
c : in std_logic_vector(ctlSiz-1 downto 0);
x : out std_logic_vector(wSiz-1 downto 0);
v : out std_logic);
end alu;
architecture a1 of alu is
signal result: std_logic_vector(wSiz downto 0);
signal ax, bx: std_logic_vector(wSiz downto 0);
begin
ax <= '0' & a; bx <= '0' & b;
with c select
result <= ax
when "000" ,
bx
when "001" ,
(not ax)+1
when "010" ,
(not bx)+1
when "011" ,
ax+bx
when "100" ,
ax+bx
when "101" ,
ax-bx
when "110" ,
bx-ax
when others;
x <= result(wSiz-1 downto 0);
v <= '1‘ when (c = "010" and a = "1000")
or (c = "011" and b = "1000")
or (c = "100" and result(wSiz) = '1')
or (c = "101" and a(wSiz-1) =b(wSiz-1) and a(wSiz-1) /= result(wSiz-1))
or (c = "110" and a(wSiz-1)/=b(wSiz-1) and a(wSiz-1) /= result(wSiz-1))
or (c = "111" and a(wSiz-1)/=b(wSiz-1) and b(wSiz-1) /= result(wSiz-1))
else '0';
end a1;
c=0 means x=a, c=1 means x=b,
c=2 means x= -a, c=3 means x=-b,
c=4 means x=a+b (unsigned),
c=5 means x=a+b (signed),
c=6 means x=a-b,
c=7 means x=b-a
v bit signals
arithmetic error
3.‹#› - Jon Turner - 5/24/2016
Alternate Architecture
architecture arithuv_arch of arithuv is
signal result: STD_LOGIC_VECTOR(4 downto 0);
signal ax, bx: STD_LOGIC_VECTOR(4 downto 0);
signal en_a, en_b, neg_a, neg_b: STD_LOGIC;
begin
process(a,b,c,en_a,en_b,neg_a,neg_b) begin
en_a <= '1'; en_b <= '1'; neg_a <= '0'; neg_b <= '0';
v <= '0';
case c is
when "000" => en_b <= '0';
when "001" => en_a <= '0';
when "010" => en_b <= '0'; neg_a <= '1';
if a = "1000" then v <= '1'; end if;
when "011" => en_a <= '0'; neg_b <= '1';
if b = "1000" then v <= '1'; end if;
when "100" => v <= result(4);
when "101" => if a(3) = b(3) and result(3) /= a(3) then
v <= '1';
end if;
when "110" => neg_b <= '1';
if a(3) /= b(3) and result(3) /= a(3) then
v <= '1';
end if;
when "111" => neg_a <= '1';
if a(3) /= b(3) and result(3) /= b(3) then
v <= '1';
end if;
when others => -- do nothing
end case;
case statement specifies alternatives
based on signal value.
en_a high when a used
to generate result.
neg_a high to produce
a or b-a.
others required when not all
alternatives listed.
3.‹#› - Jon Turner - 5/24/2016
for i in 0 to 3 loop
ax(i) <= (a(i) xor neg_a) and en_a;
bx(i) <= (b(i) xor neg_b) and en_b;
end loop;
ax(4) <= en_a and (a(3) xor neg_a);
bx(4) <= en_b and (b(3) xor neg_b);
result <= ax + bx + (neg_a or neg_b);
x <= result(3 downto 0);
end process;
end arithuv_arch;


for-loop modifies a, b
extend a, b to 5 bits
with correct sign
Original architecture synthesizes redundant components.
Alternative architecture uses single adder and disables or
negates inputs to implement different operations.
» circuit uses about half as many circuit components as original
» synthesis report provides detailed description
3.‹#› - Jon Turner - 5/24/2016
Structural Spec. for 4 Bit Adder
entity adder4 is port(
A, B: in std_logic_vector(3 downto 0);Component definitions
required in every
Ci: in std_logic;
architecture using a
S: out std_logic_vector(3 downto 0);
component.
Co: out std_logic);
end adder4;
architecture a1 of adder4 is
component statement used
component fullAdder
to form complex circuits
port(A, B, Ci: in std_logic; S, Co: out std_logic
from simpler);
parts.
end component;
signal C: std_logic_vector(4 downto 0);
begin
C(0) <= Ci; Co <= C(4);
b0: fullAdder port map(A(0),B(0),C(0),S(0),C(1));
b1: fullAdder port map(A(1),B(1),C(1),S(1),C(2));
b2: fullAdder port map(A(2),B(2),C(2),S(2),C(3));
b3: fullAdder port map(A(3),B(3),C(3),S(3),C(4));
end a1;
Positional association of
signals. Explicit assignment
(A=>A(0)) also allowed.
3.‹#› - Jon Turner - 5/24/2016
Defining Constants
 To
define constants for use by multiple entities, use separate
package.
package commonConstants is
constant wordSize: integer := 8;
end package commonConstants;
library IEEE;
use IEEE...
use work.commonConstants.all;
entity adder is
port( A, B: in std_logic_vector(wordSize-1 downto 0);
Ci: in std_logic;
S: out std_logic_vector(wordSize-1 downto 0);
Co: out std_logic );
end adder;
...
 Local constants can be declared as part of each architecture.
 HDL bencher does not handle constants in packages correctly.
» use Options Map Package Constants/Defines
3.‹#› - Jon Turner - 5/24/2016
Structural Specs. using for-generate
begin
C(0) <= Ci;
bg: for i in 0 to 3 generate
b:
fulladder port map(A(i),B(i),C(i),S(i),C(i+1));
end generate;
Co <= C(4);
end a1;
for-generate makes it easy to
generate adder of any size.
Note: labels are required.
3.‹#› - Jon Turner - 5/24/2016