Transcript Monolithic CMOS Detectors for Tracking and the Sticky Photo-Gate Wieman RNC

Monolithic CMOS Detectors for Tracking and the
Sticky Photo-Gate
Wieman
RNC
LBNL
9-Feb-2005
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Things to cover
 Brief report on the STAR Heavy Flavor Tracker program, an inner
vertex detector to use monolithic CMOS pixel detectors
 Some work on a photo-gate, an attempted improvement on the
CMOS pixels
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Cover page from proposal just submited to STAR managment
A Heavy Flavor Tracker for STAR
Z. Xu
Brookhaven National Laboratory, Upton, New York 11973
Y. Chen, S. Kleinfelder, A. Koohi, S. Li
University of California, Irvine, California
H. Huang, A. Tai
University of California, Los Angeles, California 90095
V. Kushpil, M. Sumbera
Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic
C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak,
I. Valin, M. Winter
Institut de Recherches Subatomique, Strasbourg, France
M. Miller, B. Surrow, G. Van Nieuwenhuizen
Massachusetts Institute of Technology, Cambridge, MA 02139
F. Bieser, R. Gareus, L. Greiner, F. Lesser, H.S. Matis, M. Oldenburg,
H.G. Ritter, L. Pierpoint, F. Retiere, A. Rose, K. Schweda,
E. Sichtermann, J.H. Thomas, H. Wieman, E. Yamamoto
Lawrence Berkeley National Laboratory, Berkeley, California 94720
I. Kotov
Ohio State University, Columbus, Ohio 43210
(The contributing authors to this proposal, listed above, gratefully
acknowledge the support of their funding agencies.)
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STAR Micro Vertex Detector
 Two layers
 1.5 cm radius
 4.5 cm radius
 24 ladders
 2 cm X 20 cm each
 < 0.3% X0
 ~ 100 Mega Pixels
Purpose:
Greatly improve D
meson capability in
STAR
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Selected Detector Parameters and Specifications
Min I efficiency
98%
Accidental rate
< 100 /cm2
Position resolution
< 10 m
Number of pixels
98,304,00
Pixel dimension
30 m  30 m
Detector chip active area
19.2 mm  19.2 mm
Detector chip pixel array
640  640
Number of ladders
24
Ladder active area
192 mm  19.2 mm
Number of barrels
2
Inner barrel (6 ladders)
r = 1.5 cm
Outer barrel (18 ladders)
r = 4.5 cm
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Selected Detector Parameters and Specifications
Frame read time
4 ms
Pixel read rate, after zero suppression
63 MHz
Ladder % X0
0.26%
Cooling
Room temperature air, 1 m/s
Power
100 mW/cm2
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Conceptual mechanical design
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Photo gate purpose – to address standard pixel limitations
 With the standard CMOS pixel
array off chip CDS is required to
remove fixed pattern noise and
KTC reset noise
 In the standard CMOS pixel array
the signal is spread over multiple
diodes
 Penalty in signal to noise
 Potential advantages of photo-gate
 Use like CCD – read voltage,
transfer charge – read voltage
again and take difference. Gives on
chip CDS
 Increase signal by reducing signal
spreading to adjacent pixels. The
photo gate permits large geometry
without adding capacitance to the
sense node.
P
P-
P+
Standard diode geometry
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Chip designed and built by
Stuart Kleinfelder and Yandong Chen
UC Irvine
Photo-gate geometry
 Large photo-gate to collect large fraction of the charge on a single pixel,
directly on the p- epi layer
 Small transfer gate also directly on p- epi layer
 Small drain (minimum capacitance) connected to source follower gate (sense
node)
photo gate
transfer
gate
photo gate
0.4 m
5 nm
x
-2 m-
drain
reset gate
1 m 1 m
0.1 m
P epi 1.4x1015 1/cm3
8 m
sense node
drain
row select
gate
x = 0.4 and 0.8 m
N+ 1x1020 1/cm3
(simulation quantities)
transfer
gate
source
follower
gate
20 m
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Drain current after light injection
 Nano amp drain
current
 Rapid electron
transfer complete in 60 ns
Light injection
photo
gate
transfer
gate
drain
60 ns
Simulation using SILVACO ATLAS running on laptop. Service through eecad,
only a few 10s of dollars to run. About to change to per day cost of ~$170
Relied on Zhang Li and Wei Chen to get started
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First silicon tests
Accumulated histogram of output
signal for Fe55 X-ray test after CDS
correction
Photo-gate directly to sense node drain
Issues:


Signal spreading
Reduced gain
DC bias:
V photo-gate 0.6 V
V drain 2.4 V
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Photo-gate LED test

Used a single pixel in sector 5
(simple structure with photogate and small drain on the
edge)
 Photo-gate voltage 1 volt
 Drain voltage set by full reset
voltage

drain
Test sequence
 Reset all pixels
 Clock row and column shift
registers to select a single pixel
 Inject 2 red LED pulses
 Observe output voltage with
oscilloscope throughout
sequence

Sector 5
Photo-gate
Also did same test with sector 1
( the standard diode) for
comparison
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Measured output voltage
Pixel signal with 2 LED pulses

 Both sectors exposed to
same LED pulses, but light
attenuated for sector 1
 Sector 5 response to 1st
LED pulse much smaller
than to 2nd
 Sector 5 leakage current
ramp increases after 1st
LED pulse
 Response difference for
the two pulses in sector 5
is directly related to gate,
since sector 1 shows that
readout structures are not
affected differently by
the two pulses
 Reducing the pulse
separation did not change
effect
Standard pixel diode
1.85
Output (volts)
Photo-gate
Pulse 1
1.8
Pulse 2
1.75
4
6 10
4 10
4
2 10
4
0
time (sec)
2 10
4
4 10
Features to note
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Sector 1
Sector 5
200 s
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Photo-gate time response to two pulses the same, only amplitude difference
Pixel signal with 2 LED pulses
Adjust amplitude and overlay
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Pulse 1
8
5
10 4
Pulse 2
4 10
4
2 10
4
0
time (sec)
2 10
4
4 10
4
Sector 1
Sector 5
Signal fits:

 t
 1  exp  
 




+ plus leakage slope
  204 s
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Photo-gate
 Test chip
 Measured charge transfer (200 s)
 Can surface states explain the delay, calculate expectations
 The transfer process
 Rate of direct transfer, diffusion from gate to drain
 Rate of surface state population
 Determine density of electrons at SiO2 – Si surface
 Time for surface state decay back to conduction band
 Can this account for delay
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First step of electron collection
Gate
Drain
Diffusing electrons caught in the vertical
space charge field under the gate
Electrons distribute along the surface
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Next step – getting to the drain
Surface states
Gate
Drain
Idirect
Itrapped
Direct
drain
current
Idelayed
Trapping
current
Detrapping
drain current
d
N e( t )
dt
t

 N e( t )    N e( t )     N e t p  S t  t p d t p

Don’t need to solve equation
to check for delay
0
  

N e( t )
The number of electrons
under the gate
Determine if Idirect<<Itrapped and Idelayed is
small then signal collection is slow,
more electrons spend time bound in
surface states
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Simple diffusion transfer of electrons from gate to drain
photo-gate
Diffusion equation in 1D
d
n
dt
drain
D n
d
2
2
n
dx
n
electron density
Dn
electron diffusion constant in silicon
Solve with COSMOS FEA (~3D) –
thermal transient solution, analogous
diffusion equation
Start with uniform temperature and a heat
sink at the drain
Convert to electron diffusion
Result:
drain
N( t)
N 0 exp 


n
t
total electrons under gate
n = 120 ns
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Silicon electric field under the gate
 

 E ds

1 
  q dv
s 
Using Gaussian pill box
d
E
E( y )
y
y  N A  qe
15 1
NA  1.4  10
1
s
acceptor density
3
cm
y
V( y )

 E( y ) d y

0
d
p- epi
p- epi with n type drain
vs
2 v s   s
N A  qe
1 2
qe
 y  N A
2
s
1m
= ~ 1.0 V since no inversion charge,
ignoring work function differences
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Density of electrons at the surface left by LED
electron density distribution under the gate
LD 
Debye length
LED
The static electron density
n(y) set by condition that
diffusion and drift cancel
d
Dn  n  E( y )  n   n  0
dy
use Einstein relation
transient layer of 4000 electrons left by LED
signal under 20 m  20 m gate
 kb T 
Dn  
  n
qe


kb  T s
NA  qe
y
d
= 110 nm
2
1/e distance = 12 nm
d 
depletion depth
n ( y )  n s  exp 
d  y 

 LD 


ns 
d  Ntotal
2
LD  A g
2 v s  s
NA  qe
= 960 nm
solution
Integrate over volume
under gate to get ns
2
14 1
n s  8  10
3
cm
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Rate of capture into surface states
d
Ne  v th  n  Nst  A g  n s
dt
rate of loss of electrons into surface states, see Zhang Li and H.
Kramer
v th
electron thermal velocity
n
surface state capture cross section
Measured by C vs freq, see Sze
Nst
surface state density, from Sze
Ag
area of the capture surface
ns
electron density at the surface (from last page)
 Ne
d
Ne 
dt
st
capture
direct diffusion
st = 75 ns < n = 120 ns
2
st 
Use number of empty traps
LD
d  v th  n  Nst
 75ns
time constant for capture
Capture to surface states faster
than direct diffusion to drain
therefore surface states will affect
transfer rate
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Energy window for contributing traps – how many traps
Sze
 sd 
1
 E 
v th   n  N c exp 
k b T 


Decay time constant back to
the conduction band,
Zhang Li paper
E
trap energy separation from the conduction band
v th
thermal electron velocity
n
cross section
Nc
Effective density of conduction band states
9 1
Nst  2.6  10
2
cm
4
Nst A g  1  10
Traps already filled
More than 15 ms decay time
Number of
contributing traps
Less than 100 s decay time
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Number of empty traps is reasonable
 10000 - The number of empty traps from the Sze plot which were
empty and had a lifetime of more than 100 s
 A plausible number for the trapping time ( 75 ns )
 A plausible number for saturation with the estimated 4000 photo
generated electrons
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Leakage Current measured as a function of gate voltage
The Read Shockley Hall
leakage current from
surface states should be
large when depleted and
should diminish when
space charge is
neutralized.
Drain Current vs Photo-Gate Voltage
50
40
measured
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Id
expected
fA
20
10
0
1
0.5
0
0.5
1
1.5
2
2.5
VGate
As suggested by
Pavel. A measure of
leakage current as a
function gate voltage
down below
depletion voltage
volt
Expected region where no longer depleted, but still a puzzle
Same as a gated diode
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Density of surface states from leakage current
ni
Us  NstI v th  n 
2
Ileak  13fA
NstI  2
Reed Shockley Hall recombination rate per unit area for
fully depleted non-thermal equilibrium
not in thermal equilibrium
Measured leak
Ileak
v th  n  n i qe A g
8 1
NstI  4.2  10
16% of the Sze value used for trap capture time
2
cm
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Concluding remarks
 Some questions remain, but surface traps could explain photo-gate
behavior
 They provide delay on right order
 They seem to have right number to see saturation effects
 They are consistent with observed leakage current
 Another significant problem is the large leakage current, 10 times
larger than pixel diode
 Note, both Turchetta and Janesick tell me they have tried and
failed to make a working photo-gate in standard CMOS. Janesick
saw the same type of delayed signal
 Janesick has made photo-gates work using a special process from
Jazz Semiconductor with buried channel -- big bucks
 Will there eventually be a photo process that available to us with
buried channel?
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Evidence for saturated traps using 2 equal LED pulses?
reset

Vout
reset
closed
then
open
two equal
LED pulses
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Silvaco ATLAS compared to simple space Carge potential
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Silicon Potential Volts
1.5
1
0.5
0
0.5
0
0.2
0.4
0.6
0.8
Y (microns)
Silvaco ATLAS Vpg = 1.3 V
Silvaco ATLAS Vpg = 0.8 V
Simple Space Charge V
1
1.2
1.4
1.6
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Recombination rate at surface
= 0 if in thermal equilibrium
 p n  n 2
 s s i
Us  Nst v th  
 Est  Ei 
p s  n s  2 n i cosh 

kb  T


14 1
n s  8  10
surface recombination rate per unit area
from LED pulse
3
cm
3 1
p s  4  10
or less (SILVACO ATLAS)
3
cm
10 1
n i  1.45  10
intrinsic denstiy
3
cm
so
2
2
p s  n s  n i  n i
Totally depleted even with LED pulse
Large leakage current no recombination
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