Transcript Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth

Senior Capstone Project:
Fast Tuning Synthesizer
Member:
Advisors:
Nathan Roth
Dr. Huggins
Dr. Shastry
Mr. James Jensen
Date:
March 4, 2004
Presentation Outline
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Project Summary
Functional Description
Detailed Description
Review of Previous Work
Laboratory Results
Semester Schedule
Project Summary
• Creation of a frequency synthesizer
– Use of direct synthesis approach
Project Summary
• System Characteristics
– Output Frequencies of 3650, 3700, 3850,
3900, 4450, 4500, 4650, and 4700 MHz
– Output Power of 0 dBm, ± 3 dB
– Output Spurs < -45 dBc
– Tuning Time < 500 ns, 200 ns if possible
– Use of an External 100 MHz Reference Signal
Functional Description
100 MHz Reference
Fast
Tuning
Frequency
Synthesizer
3.6 – 4.6 GHz
Digital Input
Command
D2
D1
D0
Desired
Output
Frequency
Detailed Description
Input Module
Input Module
Resolution Modules
Resolution Modules
Basis Frequency Modules
Basis Frequency Modules
Switch Selection Module
Switch Selection Module
Output Module
Output Module
Laboratory Work - Review
• Designed and Simulated Ideal Chebyshev
Filters
– Used Insertion Loss Method
– Developed Low-Pass Filter Prototype
– Transformed to Band-Pass Filter
• Added Parasitic Effects
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–
Real Component Values
Real Inductor Responses
Microstrip Transmission Effects
Via Connections
Laboratory Work - Review
Laboratory Work - Review
Laboratory Work - Review
Laboratory Work - Review
Laboratory Work - Review
Laboratory Work - Review
Laboratory Work - Review
• Determined and Ordered Necessary Parts
Laboratory Work
• Created PCB Layouts for Filter Boards
• Fabricated, Populated, and Tested Filter
Boards
• Developed Modular Layout Plan
• Currently Creating PCB Layouts for
Components
Laboratory Work
Laboratory Work
Laboratory Work
•Dark Blue = Ideal
•Purple = S21 Simulated
•Red = S11 Simulated
•Aqua Blue = S21 Actual
•Blue/Purple = S11 Actual
Laboratory Work
•Dark Blue = Ideal
•Purple = S21 Simulated
•Red = S11 Simulated
•Aqua Blue = S21 Actual
•Blue/Purple = S11 Actual
Laboratory Work
•Aqua Blue = Ideal
•Dark Blue = S21 Simulated
•Red = S11 Simulated
•Purple = S21 Actual
•Blue/Purple = S11 Actual
Laboratory Work
•Aqua Blue = Ideal
•Red = S21 Simulated
•Dark Blue = S11 Simulated
•Purple = S21 Actual
•Blue/Purple = S11 Actual
Laboratory Work
•Light Blue = Ideal
•Red = S21 Simulated
•Aqua Blue = S11 Simulated
•Dark Blue = S21 Actual
•Purple = S11 Actual
Laboratory Work
•Aqua Blue = Ideal
•Purple = S21 Simulated
•Red = S11 Simulated
•Dark Blue = S21 Actual
•Light Blue = S11 Actual
Laboratory Work
Laboratory Work
Preliminary Spring Semester
Schedule
Week
Task
Winter Break
Research and understand phase locked loop
(PLL) theory and circuitry
Begin design of PLL system
Finalize filter design and simulations
Begin implementing as parts arrive
Full scale simulation of direct synthesis
(DS) system
Jan 19 – 25
Design of PLL system
DS system simulation
Jan 26 – Feb 1
Design PLL system
DS system simulation
Have all filters tested and built
Feb 2 – 8
Complete design of PLL system
DS system simulation
Feb 9 – 15
Simulation of PLL system
Complete DS system Simulation
Preliminary Spring Semester
Schedule
Feb 9 – 15
Simulation of PLL system
Complete DS system Simulation
Feb 16 – 22
Simulation of PLL system
Feb 23 – 29
Complete simulation of PLL system
March 1 – 7
Components Arrive, Begin Soldering, Testing,
and Biasing Components
March 8 – 14
Physical implementation of DS
March 15 – 21
Physical implementation of DS, Spring Break?
March 22 – 28
Begin DS full scale testing
March 29 – April 4
DS full scale testing
April 5 – 11
Complete DS full scale testing
April 12 – 18
April 19 – 25
Student Expo
April 26 – May 2
Present successful findings
Revised Spring Semester Schedule
March 1 – 7
Generate PCB Layout for Components
March 8 – 14
Fabricate PCBs
March 15 – 21
Spring Break/Fabricate PCBs
March 22 – 28
Solder Components to PCBs
March 29 – April 4
System Testing
April 5 – 11
System Testing
April 12 – 18
System Testing
April 19 – 25
System Testing/Student Expo
April 26 – May 2
Present successful findings
Delay Line Correlator
I
R
Cos (wt)
L
Power
Splitter
T
RF cable with measure
time delay = T
Voltage output proportional to
cos (wT)
Fast Tuning Synthesizer
• Any questions?
Laboratory Work - Review
Preliminary Bill of Materials
Part Number
Maker
Description
Qty
Price
Total
Price
HMC435MS8G
Hittite
SPDT, Hi Isolation, DC4 GHz
15
1.10
16.50
PE3512
Peregrine
Divide By 4, DC - 1.5
2
2.75
5.50
MAX2671
Maxim IC
400 MHz To 2.5 GHz
Upconverter Mixers
3
0.76
2.28
SYK-2R
Mini-Circuits
Frequency Doublers, 101000 MHz
1
29.95
29.95
HMC188MS8
Hittite
Passive Frequency
Doubler, 1.25 - 3.0 GHz
Input
1
2.94
2.94
HMC187MS8
Hittite
Passive Frequency
Doubler, 0.85 - 2.0 GHz
1
2.35
2.35
Preliminary Bill of Materials
MSA-2743
Agilent
Cascadable Silicon Bipolar
Gain Block MMIC
Amplifier
1
0.94
0.94
ABA-53563
Agilent
3.5 GHz Broadband Silicon
RFIC Amplifier
3
0.40
1.20
HMC315
Hittite
GaAs InGaP HBT MMIC
Darlington Amplifier,
DC - 7.0 GHz
3
0.97
2.91
AG604-89
WJ
Ingap HBT Gain Block
2
1.48
2.96
Kit C124A
Coilcraft
1.6 nH – 30 nH, 10 pieces
each, 2% Tol
1
80.00
80.00
Substrate
Rogers
Corporation
RO4003, .020 Mil Thick,
1.4 Mil Foil
2
32.25
64.50
Connectors
Various
End Launch, Panel
Mounts, M/M Barrels
300.00
Total
512.03