Calvin College - Engineering Department Analog Design Spring 2002
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Transcript Calvin College - Engineering Department Analog Design Spring 2002
Calvin College - Engineering Department
Analog Design
Spring 2002
Engineering 332
Professor: Paulo F. Ribeiro, SB130 X6407, [email protected]
Textbook: Sedra / Smith, Microelectronic Circuits, Fourth Edition
Lectures: 12:30-1:20PM (MWF)
SB203
Laboratory (Wednesdays 1:30-4:20 PM) SB 136 and SB28
Course objectives
To focus on the design of amplifiers, filters, oscillators, and converters with an
emphasis on design.
Topics covered
Differential and Multistage Amplifiers, Frequency Response, Feedback, Output
Stages, Analog Integrated Circuits (741), Filters and Tuned Amplifiers, Signal
Generators.
Class/laboratory schedule
2-3 lectures per week plus 3-hour laboratory.
Contribution of course to meeting the professional component
This course contributes primarily to the students' knowledge of engineering topics,
and does provide design experience.
Relationship of course to undergraduate degree program objectives
This course primarily serves students in the department. The information below
describes how the course contributes to the undergraduate program objectives.
Mastery of specific technical design skills which are key to a wide range of
electrical engineering applications. Mastery and critical evaluation of the use of
computer aided simulation tools (SPICE) as an engineering design aid.
Assessment of student progress toward course objectives
Student's design skills is assessed primarily on detailed homework and design
problems that involve the use of analytical and simulation tools such as PSPICE.
Schedule
Topics
Chapter # of classes
Differential and Multistage Amplifiers
6
6
Frequency Response
7
6
Feedback
8
6
Output Stages
9
6
Analog Integrated Circuits (741)
10
3
Filters and Tuned Amplifiers
11
3
Signal Generators
12
3
Design Part I: Chapters 6, 7
Design Part II: Chapters 8, 9, 10
Final Design: Chapter 11, 12
Spring Break March 9-18
Reading Recess April 16-17
Grading
Design Part I
Design Part II
Labs
Homework and Assignments
Participation
Final Design
20%
20%
15%
15%
10%
20%
100%
Lab Schedule:
Lab 1 – The BJT Differential Pair and Amplifications
Lab 2 – Single-BJT Amplifiers at Low and High Frequencies
Lab 3 – Principles of Feedback Using and Op-AMP Building Block
Lab 4 – Basic Output-Stage Topologies
Lab 5 – OP-AMP-RC Filter Topologies
Lab 6 – Waveform Generators
Extra Lab – Power Supply
Basic Homework Assignments (Minimum List)
Students are recommended to work out most of the problems in the back of each assigned chapter.
Additional Interactive Examples from accompanying CD and design problems will also be required to be
completed.
Chapter
6
7
8
9
10
11
12
Problems
6.1, 6.5, 6.15, 6.19, 6.33, 6.42, 6.50, 6.70, 6.77, 6.87, 6.97, 6.113
7.1, 7.7, 7.11, 7.26, 7.28, 7.38, 7.57, 7.67, 7.73, 7.85
8.1, 8.8, 8.16, 8.20, 8.32, 8.48, 8.52, 8.71
9.4, 9.14, 9.18, 9.22, 9.32, 9.37, 9.45, 9.51
Detailed Analysis of the 741 OP-AMP
Analysis of A Second Order Active Filter
Analysis of the Wien Bridge Oscillator
Observations
Choose 10
Choose 8
All laboratory and homework exercises must be turned in on time for full credit. Late assignments will be
assigned a penalty. Assignments more than one week late may be assigned a 50% penalty.
Homework and lab assignments should be prepared electronically (Word, MathCAD,
PSpice, MATLAB / Simulink, PSCAD, etc.). No handwritten assignments will be
accepted.
Differential and Multistage Amplifiers
The most widely used circuit building block in analog integrated
circuits.
Use BJTs, MOSFETS and MESFETs (metal semiconductor FET
– read 5.12 – Gallium Arsenide-GaAs Device).
The BJT Differential Pair
Connection to RC not
essential to the operation
Essential that Q1
and Q2 never enter
saturation
Use CD
Implemented by a
transistor circuit
Different Modes of Operation
Common voltage
I/2
vE = vCM-VBE
vC1 = VCC – ( ½) a I RC
vC2 = VCC – ( ½) a I RC
vC1 – vC2 = ?
Vary vCM (what happens?)
Rejects common-mode
Differential pair with a common-mode input
Different Modes of Operation
vB1 = +1
Q1
Q2
vE = 0.3
Keeps Q2 off
vC1 = VCC - a I RC
vC2 = VCC
Differential pair with a large differential input
Different Modes of Operation
Differential pair with a large differential input o opposite polarity
To that of (b)
Different Modes of Operation
Differential pair with a small differential input
Exercise 6.1
5 0.7
1
4.3
vC2 5 4.3 1
vC1 5
vE 0.7
vC2 0.7
Large-Signal Operation of the BJT Differential Pair
Equations
Which can be manipulated to yield
iE1
( vB1 vE)
iE1
IS
a
e
iE1 iE2
VT
iE1
iE2
IS
a
e
VT
iE2
e
( vB2 vB1)
VT
1 e
( vB1 vB2)
( vB2 vE)
1
VT
iE1 iE2
iE2
1
iE1 iE2
( vB1 vB2)
1 e
VT
1I
iE1
The collector
currents
can be obtained by
multiplying the
emitter currents by
Alfa, which is ver
close to unity
( vB2 vB1)
VT
1 e
1I
iE2
( vB1 vB2)
1 e
VT
I
Large-Signal Operation of the BJT Differential Pair
Relatively small
difference voltage vB1 –
vB2 will cause the
current I to flow almost
entirely in one of the two
transistors.
4.VT (~100mV) is
sufficient to switch the
current to one side of the
pair.
Small-Signal Operation
The Collector Currents When vd is applied
vd
iC1
vB1 vB2
aI
vd
vBQ1
aI
2
VBE
a I vd
2 VT 2
vd
2
iC1
aI
2
VBE
2
Interpretation: IC1 increases by ic and iC2 decreases by ic
VT
a I e
iC1
gm
IC
2
VT
VT
2 VT
vd
vd
e
a I vd
2 VT 2
vd
vd
vd
a I
ic
vBQ2
2 VT
aI
1 e
iC2
vd
VT
1 e
iC2
Multiplying by
2 VT
e
2 VT
Assuming vd<<2VT
~
a I 1
iC1
1
vd
2 VT
2 VT
vd
1
vd
2 VT
An Alternative Viewpoint
Assume I to be ideal – its incremental resistance will be infinite and vd appears across a total
resistance 2.re.
re
VT
VT
IE
I
ie
2
ic
a ie
a vd
2 re
gm
vd
2
A simple technique for
determining the signal currents
in a differential amplifier
excited by a differential voltage
signal vd; dc quantities are not
shown.
vd
2 re
If emitter resistors are included
ie
vd
2 re 2 RE
A differential amplifier with emitter resistances. Only signal quantities are shown (on color).
Input Differential Resistance
vd
ib
Rid
ie
2 re
1
1
vd
ib
1 2re 2 r
This is the resistance-reflection rule; the resistance seen between the two bases is
equal to the total resistance in the emitter circuit multiplied by the beta+1
Input Differential Resistance
Rid
1 (2 re 2 RE)
Differential Voltage Gain
iC1
IC gm
vd
IC gm
iC2
2
vC1
( VCC IC RC) gm RC
vd
vC2
( VCC IC RC) gm RC
vd
Ad
Ad
vc1 vc2
vd
2
2
gm RC
a ( 2RC)
( 2 re 2 RE)
RC
~
re RE
The voltage gain is equal to the
ratio of the total resistance in the
collector circuit (2RC) to the total
resistance in the emitter circuit
(2re+2RE)
vd
2
IC
aI
2
Equivalence of the Differential Amp. To a Common-Emitter Amp.
Differential amplifier fed in a
complementary manner
(push-pull or balanced)
Base of Q1 raised
Based of Q2 lowered
Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). This
equivalence applies only for differential input signals. Either of the two common-emitter
amplifiers in (b) can be used to evaluate the differential gain, input differential resistance,
frequency response, and so on, of the differential amplifier.
Equivalent Circuit Model of a Differential Half-Circuit
RC ro
Ad gm
RC ro
Common-Mode Gain
Assuming symmetry
Common-mode
half-circuits
vc1
vCM
vc2
vCM
Assuming non-symmetry
vo
RC RC
2 R RC
v1 v2
vCM
Ad ( v1 v2) Acm
2
v1 v2
2
2 R re
vCM
a RC
2 R
a RC
2 R
If output is taken single-endedly
Acm and the differential gain Ad
We can define CMRR
Acm
Acm
a RC
CMRR
a RC
2 R
Ad
Acm
Ad
1
2
gm RC
CMRR gm R
a1
Input Common-Mode Resistance
Ricm
r
vCM
vCM
ro
2 . Ricm
Ricm =
Equivalent common-mode half-circuit
Since the input common-mode resistance
is usually very large, its value will be
affected by the transistor resistances
R0 and r
Nehemiah (Chief-Engineer of Wall Reconstruction)
God Calls Us to be agents:
Of Peace and Reconciliation
For Justice
For the Flourishing of the Natural Creation
For Beauty
For Knowledge
For the Growth of other people
Example 6.1 – Class Discussion
Example 6.3
a) vE b) gm c) iC d) vC e) vc1-vc2 f) gain at 1000Hz
I 1
VCC 15
RC 10
a 1
vB1( t) 5 0.005 sin 2 1000 t
vB2( t) 5 0.005 sin 2 1000 t
vBE 0.7
at 1mA
a)
VBE 0.7 0.025 ln
0.5
1
vE 5 VBE
VBE 0.683
vE 4.317
b)
gm
IC
gm 20
VT
c)
iC1( t) 0.5 gm 0.005 sin 2 1000 t
iC2( t) 0.5 gm 0.005 sin 2 1000 t
0.6
iC1( t ) 0.5
iC2( t )
0.4
0.3
0
0.001
0.002
0.003
t
0.004
0.005
d)
vC1( t ) ( VCC IC RC) 0.1 RC sin 2 1000 t
vC2( t ) ( VCC IC RC) 0.1 RC sin 2 1000 t
11
vC1( t )
vC2( t )
10
9
0
0.001
0.002
0.003
0.004
0.005
0.003
0.004
0.005
t
e)
2
vC2( t ) vC1( t )
0
2
0
0.001
0.002
t
Example 6.4
100
Delta_RC 0.02
Delta_IS 0.1
Delta_ 0.1
I 100
From Eq. 6.55
2
Delta_RC
Delta_IS
VOS VT
RC IS
2
2
VOS 25 ( 0.02) 0.1
IB
I
2 1
Delta_
IOS IB
2
VOS 2.55
IB 0.495
A
4
IOS 4.95 10
50nA
A
Finally, brothers, whatever is true, wherever is noble, whatever is right,
what ever is pure, whatever is lovely, whatever is admirable – if anything is
excellent or praiseworthy – think about such things.
Phil. 4:8
I gladly admit that we number among us men and women whose modesty,
courtesy, fair-mindedness, patience in disputation and readiness to see an
antagonist's point of view, are wholly admirable. I am fortunate to have known
them. But we must also admit that we show as high percentage as any group
whatever of bullies, paranoiacs, backbiters, mopes, milksops, etc.. The
loutishness that turns every argument into a quarrel is really no rarer among us
than among the sub-literate; the restless inferiority-complex (“stern to inflict”
but not “stubborn to endure”) which bleeds at a touch but scratches like a
wildcat is almost as common among us as among schoolgirls.
CS Lewis.
Biasing In BJT Integrated Circuits
Many resistors, transistors and capacitors makes impossible to use
conventional biasing methods
Biasing in IC is based on the use of constant-current sources
The Diode-Connected Transistor
Shorting the base and the collector of a BJT results in a twoterminal device having an I-v characteristic identical ot the
iE-vBE of the BJT.
i
i
1
1
i
i
Since the BJT is still in active mode (vCB=0 results in an
active mode operation) the current I divides between base
and collector according to the value of the BJT Beta.
Thus, the BJT still operates as a transistor in the active mode.
This is the reason the I-v characteristics of the resulting
diode is identical to the iE-vBE relationship of the BJT
Exercise 6.5
R incremental = r // (1/gm) // ro
1
r
gm
1
r
Rinc
r
r
ro
1
gm
1
gm
1
gm
r
r
ro
1
ro
ro
re ro
re ro
re
Rinc
25
0.5
Rinc 50
The Current Mirror
Io
IO
1
IE
IO
IREF
2
IREF
1
1
2
1
IE
Finite Beta and Early Effect
IO
2
V O V EE V BE
1
2
VA
1
I REF
Exercise 6.6
VEE 5
Rout
VBE 0.7
IO
at
IREF
100
5
Rout 1 10
IREF
at
VO
VB
IREF
1
IREF 0.001
VA
ro
Rout
100
VO VEE VBE
VO 4.3
4
IO 9.804 10
2
VO 5
IO5 IO
5 ( 4.3)
Rout
3
IO5 1.073 10
A Simple Current Source
I REF
V CC V BE
R
Exercise 6.7
IO
IREF 0.001
IREF
VCC 5
100
neglect the effects ro and finite Beta
R
at
VCC VBE
IREF
VO 3
R 4.3 10
IREF
1 2
VA 50
ro
3
IO
VBE 0.7
VO VBE
ro
VA
IREF
4
ro 5 10
3
IO 1.026 10
Get wisdom, get understanding; do not forget my words or swerve from them. Do
not forsake wisdom, and she will protect you; love her, and she will watch over you.
Wisdom is supreme; therefore get wisdom. Though it cost all you have, get
understanding. Esteem her, and she will exalt you; embrace her, and she will honor
you. She will set a garland of grace on your head and present you with a crown of
splendor. Prov. 4:4-8
However, this impulse to pursue the intellectual life must be kept "pure and
disinterested," for the alternative is to "come to love knowledge-our knowingmore than the thing known: to delight not in the exercise of our talents but in the
fact that they are ours, or even in the reputation they bring us".
We must not think Pride is something God forbids because He is offended at it, or that
Humility is something He demands as due to His own dignity -- as if God Himself was
proud. He is not in the least worried about His dignity. The point is, He wants you to
know Him: wants to give you Himself. And He and you are two things of such a kind
that if you really get into any kind of touch with Him you will, in fact, be humble -delightedly humble, feeling the infinite relief of having for once got rid of all the silly
nonsense about your own dignity which has made you restless and unhappy all your
life. He is trying to make you humble in order to make this moment possible: trying to
take off a lot of silly, ugly, fancy-dress in which we have all got ourselves up and are
strutting about like the little idiots we are.
Current-Steering Circuits
I REF
V CC V EE V EB1 V BE2
R
IC Circuits
2 power supplies
IREF is generated in the branch of
the diode-connected transistor Q1,
resistor R, and the diode-connected
transistor Q2.
Generation of a number of cross currents.
Exercise 6.9
Comparison With MOS Circuits
1 - The MOS mirror does not suffer from the finite Beta
2 – Ability to operate close to the power supply is an important issue on IC design
3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L
4 - VA lower for MOS
Improved Current-Source Circuits
IREF
IO
2
I
1
2 E
1
1
IE
IO
IREF
IREF
1
1
1
2
2
1
VCC VEB1 VBE3
R
2
2
The Wilson Current Mirror
Output resistance equal
ro
2
A factor greater the then simple
Current source
Disadvantage: reduced output swing.
Observe that the voltage at the collector at
Q3 has to be greater than the negative
supply voltage by
(vBB1 = VCEsat-3), which is about a volt.
Exercise 6.10
2
1
2
1
2
I E
2
I E
1
1
2 I E
I E
I E
IREF
IO
I E
1
IE
2
2 I
E
1
2
1
2
1 2
1
IE
IE
1
1
2
IO
IE
2 2
IREF
IO
IREF
IE
~
1
1
2
2
Widlar Current Source
It differs from the basic current mirror in an
important way: a resistor RE is included in
the emitter lead of Q2. Neglecting the base
current we can write:
IREF
VB1 VT ln
IS
IO
VB2 VT ln
IS
IREF
VB1 VB2 VT ln
IO
VB1
VB2 IO RE
IREF
IO RE VT ln
IO
Example 6.2
Example 6.3
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 1st stage gain
-- Assuming 100
V
100W
re1 re 2 I TE .25
25
Model Eqs. on Pg. 263
re
r
gm
( VI CT ) ( I
VT
E
( 1 )
)
r 1 r 2 ( 1)( re )
101 *100 10.1kW
Rid r 1 r 2 20.2kW
In the same manor
Ri 2 r 4 r 5
Ri 2 2 ( 1) r
2 (101 25) 5.05kW
Current sources for biasing amplifying stages
By Justin Jansen
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 1st stage gain
Total collector resistance
1
Ri2
Total emitter resistance
A1
vo 1
vid
I C RC _ Total_ R
I E RE _ Total_ R
Ri 2 ||( R1 R2 )
re1 re 2
5.05kW||40 kW
200W
22.4 VV
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 2nd stage gain
Ri3
Ri 3 ( 1)( R4 re7 )
re 7
VT
IC
25
1
25W
Ri 3 101 (2.3kW 25W)
234.8kW
re4 and re5 calc. before
A2
R3 || Ri 3
re 4 re 5
3 kW||234.8 kW
50W
59.2
V
V
Potential gain is halved b/c converting to single-ended output
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 3rd stage gain
Purpose is to allow amplified
signal to swing negatively
re8
Ri4
25
5
5W
Ri 4 ( 1)( re8 R6 )
101(5 3000) 303.5kW
A3
vo 3
vo 2
R5 || Ri 4
re 7 R4
15.7 kW||303.5 kW
2.325kW
6.24 VV
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 3rd stage gain
A4
vo
vo 3
3000
3005
R6
re 8 R6
.998 VV
Overall Gain
A
Output Resistance
vo
vid
A1 A2 A3 A4 8513 VV
Ro R6 || (re8
R5
1
) 152W
1 Samuel 7:7-12
When the Philistines heard that Israel had assembled at Mizpah, the rulers of the
Philistines came up to attack them. And when the Israelites heard of it, they were afraid
because of the Philistines.
[8] They said to Samuel, "Do not stop crying out to the Lord our God for us, that he may
rescue us from the hand of the Philistines."
[9] Then Samuel took a suckling lamb and offered it up as a whole burnt offering to the
Lord. He cried out to the Lord on Israel's behalf, and the Lord answered him.
[10] While Samuel was sacrificing the burnt offering, the Philistines drew near to
engage Israel in battle. But that day the Lord thundered with loud thunder against the
Philistines and threw them into such a panic that they were routed before the Israelites.
[12] THEN SAMUEL TOOK A STONE AND SET IT UP BETWEEN MIZPAH AND SHEN. HE
NAMED IT EBENEZER, SAYING, "THUS FAR HAS THE LORD HELPED US."
"The only people who achieve much are those who want knowledge
so badly that they seek it while the conditions are unfavorable.
Favorable conditions never come."
The BJT Differential Amplifier With Active Load
vo
g m v d Ro
ro2 ro4
Ro
ro2
ro2 ro4
ro
Ro
vo
2
vo
g m ro
vd
2
IC
gm
ro
VT
g m ro
VA
ro4
ro
g m v d
2
VA
IC
IC
2 r
I
2
constant for a given transitor
VT
I
Ri
ro
Gm
gm
2
VT
The Cascode Configuration
The Cascode Configuration
How shall a young man be faultless in his way?
By keeping to your words.
With all my heart I seek you;
let me not stray from your commands.
Within my heart I treasure your promise,
that I may not sin against you.
Blessed are you, O Lord;
teach me your statutes.
With my lips I declare
all the ordinances of your mouth.
In the way of your decrees I rejoice,
as much as in all riches.
Ps 119: 9-14
Experience, the most brutal of teachers; but you learn, my God do
you learn.
C.S. Lewis
BJT Single Stage Common-Emitter Amplifier
MOSFET Operation
MOS Differential Amplifiers – MOS Differential Pair
MOS Differential Amplifiers – Offset Voltage
MOS Differential Amplifiers – Current Mirrors
Problem 6.1
RC 3000
at
vBE 0.7
iC 0.0005
vE vCM vBE
iC1
1
iC
vC1 VCC iC1 RC
iC 0.001
vCM 2
vBE 0.7 0.025 ln
0.5
1
vE 2.683
4
iC1 4.95 10
vC1 3.515
VCC 5
vBE 0.683
100
Problem 6.15
vd 0.1
ie
re 25
vd
2 ( re RE)
RE 100
4
3
iE1 1.4 10
iE2 IE ie
iE2 6 10
vc1 ie RC
vc1 2
vc2 vc1
vd
RC 5000
ie 4 10
iE1 IE ie
Ad
IE 0.001
4
Ad 40
vc2 ie RC
vc2 2
BJT Differential Amplifier Laboratory
Purpose
The purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuit’s behavior needs to be
modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and
simulated results is required for the relative validity of the models.
This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.
Procedure
Construct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power
Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).
Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current
and collector current. From these current values calculate .
Figure 1) Circuit for testing transistor value
Figure 2
Next construct the amplifier
circuit shown in Figure 2.
All transistors are
MPQ2222 Bipolar Junction
Transistors. Use PSpice to
construct the circuit.
Measure the DC values at the
collector of Q1 and Q2. Do
the measured values agree
with theoretical ones.
Measure the DC value at the
emitter of Q1 and Q2. Do
the measured value agree
with the theoretical one.
Indicate the inverting and noninverting output.
Input an AC signal into Q1 of
your circuit at frequencies .
What is the single voltage
gain of your circuit?
Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC
operating point of the amplifier. Bias point voltages are measured and then compared to
the bias points produced by the PSpice simulation. Record DC bias point data.
Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031 V
and apply to one of the input terminals and the other terminal remained grounded, as shown
in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A Multi-Meter the
output of the amplifier to observe input signal frequencies. Determine the corner frequency
(3-dB point) of the output and compared with the corner frequency generated with an AC
sweep in PSpice. Plot the PSpice AC sweep simulation.
Next calculate the differential mode voltage gain, AV-dm, from the laboratory data and
compare to the AV-dm predicted by the PSpice simulation and theoretical equations. Both
inputs are tied together to create a common mode signal on the input terminals. The output
voltage is then used to calculate the common mode voltage gain, AV-cm, and then compared
to the AV-cm predicted by the PSpice simulation and theoretical equations. From these
values the common mode rejection ratio (CMRR) should be calculated for each case.
Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The
resistors were all given standard unbridged values and were allowed to vary uniformly
within 5% of the nominal resistor value. The transistors should be given a nominal value
(say 175) and allowed to vary uniformly to +/- 100. The variations of differential and
common mode gains should be graphed on two histograms.
Analysis / Questions
What are the values of for the first transistor?
(typical values of range from approximately 125 to 225)
With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the
PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there
would be little change in values from one transistor to the next, making the previous assumption
reasonably valid.
How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation?
What is the reason for the small differences between measured and predicted voltages?
• Can a truly thinking person be a Christian?
• Does the Gospel conflict with scientific knowledge
and modern discoveries in other fields?
• How can Christians achieve intellectual / scientific
integrity?
Found in Faith-Lost in Matters of Learning and Intellectual Integrity.
The supreme end of education is expert discernment in all things - - the
power to tell the good from the bad, the genuine from the counterfeit,
and to prefer the good and the genuine to the bad and the counterfeit.
Samuel Johnson
Independence / obedience, honesty, humility, fairness…
Let integrity and uprightness preserve me.
Psalms, 25,21
Exercises 6.17
An Active-Loaded CMOS Amplifier
Exercise 6.19
Example 6.5 SPICE Simulation of a Multistage Amplifier
Frequency Response
S-Domain Analysis Poles and Zeros
N 40
z1 7 3 jj
jj 1
z2 0
i 0 N
p1 3 3 jj
p3 7
j 0 N
p2 3
p4 0 2 jj
e 10.1 i 0.4
j 10.1 j 0.4
i
f ( e w)
M
i j
[ ( e z1 w jj) ( e z2 w jj) ]
( e w jj p1) ( e w jj p2) ( p3 w jj e) ( e w jj p4)
f e j
i
M
Bode Plots
Example 7.2
Teach me your way, O Lord,
and I will walk in your truth;
give me an undivided heart,
that I may fear your name.
Ps. 86:11
"As for you, my son Solomon, know the God of
your father, and serve Him with a whole heart
and a willing mind; for the LORD searches all
hearts, and understands every intent of the
thoughts.
(1 Chr. 28:9)
COOPERATIVE LEARNING
Positive interdependence. Team members are obliged to rely on one another to
achieve the goal.
Individual accountability. All students in a group are held accountable for doing
their share of the work and for mastery of all of the material to be learned.
Face-to-face interaction. Although some of the group work may be parcelled out
and done individually, some must be done interactively, with group members
providing one another with feedback, challenging one another's conclusions and
reasoning.
Appropriate use of collaborative skills. Students are encouraged and helped to
develop and practice trust-building, leadership, decision-making, communication, and
conflict management skills.
Group processing. Team members set group goals, periodically assess what they are
doing well as a team, and identify changes they will make to function more
effectively in the future.
COOPERATIVE LEARNING
"What is the main idea of...?"
"What if...?"
"How does...affect...?"
"What is the meaning of...?"
"Why is...important?"
"What is a new example of...?"
"Explain why...."
"Explain how...."
"How does...relate to what I've learned before?"
"What conclusions can I draw about...?
"What is the difference between ... and ...?"
"How are ... and ... similar?"
"How would I use ... to ...?"
"What are the strengths and weaknesses of...?"
Frequency Response
Exercise 7.1
The Amplifier Transfer Function
The Three Frequency Bands (AM, wl, wh, BW, GB)
The Gain Function A(s) and the Low-Frequency Response
A(s )
A M FL( s ) FH( s )
A(s )
AM
A L( s )
A M FL( s )
A H( s )
A M FH( s )
L H
L
2
2
P1 P2
2
2
2 Z1 2 Z2
this relationship can be extended to any number of poles and zeros
one of the poles can be dominant and the expression is simplied
Low-Frequency Response
H
1
1
2
P1
1
2
P1
2
2
Z1
2
2
Z1
Becoming An Engineer
Competence
Responsibility
Integrity
Writing
Speaking
Pr. 1:7
Writing
General Suggestions
1.
Learn All You Can (Furnish Your Mind)
2.
Think Hard About The Subject (Exercise Your Mind)
(Interesting, Creative Ideas)
3.
Avoid Distractions (Quiet Your Mind)
4.
Take A Break (Refresh Your Mind)
5.
Save Time For Reflection (Free Your Mind)
6.
Associate With Creative People (Stimulate Your Mind)
7.
Keep Writing In Your Log Book (Tune In To Your Mind)
8.
Notice Your “Crazy” Ideas (Respect Your Mind)
9.
Be Quick To Question Authority/Professor (Alert Your Mind)
10. Trust God (Surrender Your Mind)
Graphics
Creation, Fall and Redemption:
A Controls Systems Perspective
CREATION
Word of
God
(Laws,
Commands,
Structure)
Creation
Providence
FALL
+
REDEMPTION
Cultural Mandate
+
Cosmos
Human Life
History, Culture
Redemption
+
Unfolding
Redeeming
Creation
Redeemed
Creation
+
Consummation
Language exists to communicate whatever it can communicate. Some things it
communicates so badly that we never attempt to communicate them by words if
any other medium is available.
C.S. Lewis
Mathematics
Creation, Fall and Redemption:
A Mathematical Perspective
( 0) God (Universe )
Creation
(Universe ) dx. dy. dz
( Good )
( God ' s... Will ) ( Evil )
Fall
d
( Evil ) ( Sin )
dt
( Man ' s... Sins)
Redemption
( Death )
( Jesus' ... Suffereing... & ... Re surection )
( Death )
( Death ) ( Eternal... Life )
The reason that some intuitive minds are not mathematical is that they cannot at all turn their
attention to the principles of mathematics. But the reason that mathematicians are not intuitive is
that they do not see what is before them …since they are accustomed to the exact principles of
mathematics… and are lost in matters of intuition where the principles do not allow of such
arrangement.
Blaise Pascal
Using Short-Circuit and Open Circuit Times Constants
For the Approximate Determination of L and H
Open Circuit time Constants
H
1
CiRio
i
Dominant Pole Exists
Short Circuit time Constants
L
CiRis
1
i
Example 7.5 - Study
Low-Frequency Response of the Common-Source Amplifier
Vg ( s )
Rin
Vi( s )
Rin Rs
s
1
CC1 Rin R
highpass function
Cc1 introduces a zero at zero frequency
and a real pole at p1
P1
1
CC1 Rin R
Low-Frequency Response of the Common-Source Amplifier
Next
Id ( s )
Vg ( s )
I( s )
1
Zs
gm
g m Vg ( s )
Id ( s )
YS
1
1
ZS
RS
YS
g m YS
s CS
s
g m Vg ( s )
Id ( s )
1
CS RS
g 1
m R
S
s
CS
Z
CS
gm
1
CS RS
introduces a zero at
P2
ZS
at infinite, which means Vo zero
CS
1
RS
1
Rs 1
gm
CS
1
RS g
m
Low-Frequency Response of the Common-Source Amplifier
ro RD
approximation is valid
after Thevenin's theorem and some manipulation
Vo ( s )
s
Id ( s ) Parallel RD ro RL
s
P3
1
CC2 RL
R r
D o
RD ro
CC2
1
CC2
RL
RD ro
R r
D o
introduces a zero at zero freq.
and a real pole a
W P3
Low-Frequency Response of the Common-Source Amplifier
A L( s )
AM
Vo ( s )
Vi( s )
Rin
A M
s
s Z
s
s P1 s P2 s P3
g m Parallel RD ro RL
Rin R
Low-Frequency Response of the Common-Source Amplifier
Design of the Coupling Cc1 and Cc2
and Bypass Capacitors Cs
To place the lower 3-db frequency wl at the specified value.
Exercise 7.7
The frequency of the zero is given by eq. 7.37
Z
1
CS RS
CS
The frequency of the pole is given by eq. 7.38
gm
p
gm
CS
1
RS
Analysis of the Common-Emitter Amplifier
Analysis of the Common-Emitter Amplifier
A MOSFET common-source amplifier (a), and a BJT common-emitter amplifier (b). here, Vs and Rs represent the
Thévenin equivalent of the circuit at the input side, including the output circuit of the preceding amplifier stage (if
any) and the bias network of the transistor Q (if any). Similarly, RL represents the total resistance between the drain
(the collector) and signal ground. Although signal ground at the source (emitter) is shown established by a large
capacitor, this is not necessary, and the circuits can be used to represent, for instance, the differential half-circuit of a
differential pair.
(a) Equivalent circuit for analyzing the high-frequency response of the amplifier circuit of Fig. 7.15(a). Note that
the MOSFET is replaced with its high-frequency equivalent-circuit. (b) A slightly simplified version of (a) by
combining RL and ro into a single resistance R’L = RL//ro.
Chapter 8 - Feedback
1 - Desensitize The Gain
2 - Reduce Nonlinear Distortions
3 - Reduce The Effect of Noise
4 – Control The Input And Output Impedances
5 – Extend The Bandwidth Of The Amplifier
Chapter 8 – Feedback
The General Feedback Structure
A
xs
xi
xf
xo
A
1 A
feedabck factor
loop gain
amount of feedabck
xo
A xi
xi
xs xf
xf
xo
Af
xo
A
xs
1 A
The General Feedback Structure
Exercise 8.1
4
A f 10
A 10
a)
b)
Af
c)
Amount_Feedback 20 log 1 A
Amount_Feedback 60
R1
R1 R2
A
d)
1 A
Vs 1
Vo A f Vs
Vf Vo
1
given
Vo 10
Vf 0.999
Vi Vs Vf
4
Vi 10 10
A
Af
1 A
e)
Find
R1
R1 R2
0.1
4
A 0.8 10
0.1
R2
R1
9
10 9.998
10
100 0.02
A f
A
1 A
A f 9.998
The General Feedback Structure
Exercise 8.1
Some Properties of Negative Feedback
Gain Desensitivity
Af
A
1 A
deriving
dAf
dA
(1 A )
dividing by
2
dAf
1
Af
(1 A )
Af
A
1 A
dA
A
The percentage change in Af (due to variations in some circuit parameter) is smaller than the
pecentage cahnge in A by the amount of feedback. For this reason the amount of feedback
1 A
is also known as the desensitivity factor.
Some Properties of Negative Feedback
Bandwidth Extension
Some Properties of Negative Feedback
Noise Reduction, Reduction of Nonlinear Distortion
The Four Basic Feedback Topologies
The four basic feedback topologies: (a) voltage-sampling series-mixing (series-shunt) topology; (b) current-sampling shunt-mixing
(shunt-series) topology; (c) current-sampling series-mixing (series-series) topology; (d) voltage-sampling shunt-mixing (shunt-shunt)
topology.