ECE 545 Project 2 Specification

Project 2 (15 points) – due Tuesday, December 19, noon Application: Technology: Target: cryptography OR digital signal processing optimized version with structural optimizations for minimum area and maximum throughput/area ratio ASIC

revised

synthesizable code scripts for Design Analyzer and PrimeTime

synthesis with Design Analyzer timing analysis with PrimeTime design equivalence with Formality

Sources

Synopsys documentation and examples available at http://ece.gmu.edu/courses/ECE545/viewgraphs_F06/synopsys.htm

George Michael,

PrimeTime: Static Timing Analysis Tool

, scholarly paper, George Mason University, December 2006 (available on the course web page)

Optimization Criteria

Architecture 1

Minimum

Total Circuit Area Architecture 2

Maximum ratio

Throughput divided by Total Circuit Area

Project 2 - Platforms & tools

Target devices:

standard-cell ASICs

Libraries:

90 nm TCBN90G TSMC library 130 nm TCB013GHP TSMC library

Tools:

VHDL Simulation: Aldec Active HDL or ModelSim VHDL Synthesis: Timing Analysis: Synopsys Design Analyzer Synopsys PrimeTime Design Equivalence: Synopsys Formality

Task 1

Select two or more versions of your synthesizable VHDL code developed as a part of Project 1 (a & b), and optimized for a) minimum area b) maximum throughput to area ratio.

Use the results of your earlier experiments with FPGAs

or

consider multiple values of circuit parameters (such as parameter

d

for encryption) in order to find a circuit with the maximum throughput to area ratio.

Revise your codes in such a way that they can be synthesized using Synopsys Design Analyzer with TSMC libraries of standard cells.

Task 2

Verify your revised codes using functional simulation based on a comprehensive testbench developed as a part of Project 1.

Task 3

Prepare Design Analyzer scripts which will enable you to synthesize all considered versions of your codes optimized for a) minimum area b) maximum throughput to area ratio.

Identify commands and parameters (such as defining target clock period) that you can attempt to modify in order to obtain the synthesized circuit with a) minimum area b) maximum clock frequency c) maximum ratio of throughput to latency.

Task 4

Synthesize your codes using Synopsys with the following libraries: 1. Synopsys with the 90 nm TCBN90G TSMC library 2. Synopsys with the 130 nm TCB013GHP TSMC library Repeat synthesis for multiple values of parameters identified in Task 3, in order to find parameters leading to circuits with the a) minimum area b) maximum throughput to area ratio.

Draw diagrams showing the dependence between the target clock frequency and the actual clock frequency and area.

Task 5

Synthesize your best codes optimized for a) minimum area b) maximum throughput to area ratio using Synplicity Synplify Pro and the following FPGAs as target devices: 1. Xilinx Spartan 3 2. Xilinx Virtex II In both cases use the smallest device of a given family capable of holding the entire circuit with up to 70% of CLB slice utilization.

Task 6

Compare the maximum clock frequency between circuits synthesized using 1. Xilinx Spartan 3 FPGA vs. ASIC with 90 nm TSMC library 2. Xilinx Virtex II FPGA vs.

ASIC with 130 nm TSMC library Explain the obtained results.

Task 7

Prepare PrimeTime scripts to be used to analyze your circuits.

Use templates suggested by George Michael and the TA, and modify them to match your code and the types of analyses you are planning to perform.

Task 8

Using PrimeTime - determine the critical paths in your circuits optimized for a) minimum area b) maximum throughput to area ratio.

Mark these critical paths in your block diagram.

Analyze all timing reports generated by your script and identify any violations of timing constraints.

For the obtained violations, explain the meaning of the violation by drawing a corresponding simplified timing waveform.

Task 9

Using PrimeTime Repeat your analysis for the case of input and output delays equal to the 20%,40%, 60%, and 80% of the clock period.

Identify which values of input and output delays lead to violations of the timing constraints.

Explain why? How would you modify your circuit to eliminate these timing violations?

Task 10

Using Formality, determine the design equivalence between the original VHDL code and the optimized netlist obtained from synthesis.

Repeat your analysis for the circuits optimized for a) minimum area b) maximum throughput to area ratio.

In case of mismatches, modify your VHDL code, resynthesize it, and check for equivalence again.

When introducing changes try to follow strictly rules for writing a synthesizable VHDL code.

Task 11

In case you have obtained no mismatches in Task 8 without the need to modify your codes, generate the mismatches on purpose by making a small modification in your VHDL code and comparing it with a netlist corresponding to the unmodified code.

The possible modifications may include replacing a register by a direct connection between its input and output, changing the connections in your circuit, modifying a sensitivity list in a process, etc.

Tips & Hints (1)

Each entity and each package should be placed in a different file.

The name of each file should be exactly the same as the name of an entity or package it contains.

Arrange entity names in the bottom-up order (the top-most entity at the end of the list) and define this list in your script using the command blocks = { entity1, entity2, …, entityN}

Tips & Hints (2)

Use only one clock in your entire design.

Use an identical name for the clock signal in all your entities and packages (including declarations of components).

Use the same clock name in all clock-related commands of your script, such as create_clock , set_clock_transition , etc.

Tips & Hints (3)

Avoid advanced features, such as: • multiple clocks, • gated clocks, • multicycle paths, • circular feedback loops containing only combinational logic.

Although these features are supported by Synopsys, their correct use requires additional knowledge and experience that are beyond the scope of ECE 545.

Tips & Hints (4)

Create a project directory in your main user directory.

Create the following subdirectories in the project directory: db, docs, log, reports, scripts, tb, vhdl.

Place all your synthesizable source files in the vhdl directory, and your testbench files in the tb directory.

Place your scripts in the script directory.

Define at least the following directories close to the beginning of your script: src_directory, report_directory, db_directory .

Tips & Hints (5)

Do not change values of the constraint conditions specified using the following script commands: set_clock_latency 1.0 find(clock, "clk") set_clock_transition 0.01 find(clock, "clk") set_clock_uncertainty -setup 0.1 find(clock, "clk") set_clock_uncertainty -hold 0.1 find(clock, "clk") set_load 0 all_outputs() set_wire_load_model -library tcb013ghptc -name "TSMC8K_Fsg_Conservative“ You can change a clock name “clk” within these commands if necessary.

These constraints are required to be the same for all students.

Tips & Hints (6)

Using commands set_input_delay & set_output_delay set input dalay and output delay initially to 20% of the target clock period.

Modify these values as a part of Task 9.

Tips & Hints (6)

Change your current directory to your log directory before you execute design_analyzer .

After executing your script within design_analyzer , analyze the contents of log files generated in the directory log .

These files contain the exact description of warnings and errors generated during synthesis.

Please do your best to eliminate all errors and majority of warnings generated by the scripts and written to the log files.

Project Deliverables Task 1

Source codes of all synthesizable files you have developed in order to meet the project specification. Description of any changes you have had to make in these codes in order to a. get your codes synthesized using Synopsys with TSMC libraries, b. eliminate all synthesis errors and minimize the number of synthesis warnings.

Project Deliverables Task 2

Source code of the comprehensive testbench capable of verifying the operation of your entire circuit.

Input files containing test vectors, and output files containing reports from simulation.

Timing waveform from functional simulation, demonstrating the correct operation of the circuit.

Project Deliverables Task 3

All scripts developed as a part of Task 3, and used in Task 4.

Project Deliverables Task 4

The detailed timing and area results obtained for all synthesized circuits, including • maximum clock frequency • area • maximum throughput • maximum throughput/area ratio Values of parameters leading to circuits with the a) minimum area b) maximum throughput to area ratio.

Project Deliverables Task 4 – cont.

Diagrams showing the dependence between the target clock frequency and the actual clock frequency and area.

Possible explanation of the obtained results.

Project delivarables Tasks 5 & 6

The detailed timing results for FPGAs, and their comparison with the timing results for ASICs.

Explanation of differences.

Project Deliverables Task 7

All PrimeTime scripts developed in order to analyze your circuits.

Project Deliverables Task 8

Block diagrams with marked critical paths.

All timing reports generated by your script and the summary of the obtained violations of timing constraints.

For the obtained violations, simplified timing waveform explaining the meaning of these violations.

Project Deliverables Task 9

Reports from timing analysis for the case of input and output delays equal to the 20%,40%, 60%, and 80% of the clock period.

Values of input and output delays leading to violations of the timing constraints.

Explanation how would you modify your circuit to eliminate these timing violations.

Project Deliverables Task 10

Short description of the results obtained from Formality.

Description of any changes you have had to make in your codes in order to pass the equivalence check.

Project Deliverables Task 11

Short description of the artificially generated mismatches and the way of reporting them by the tool.

All Projects – Honor Code Rules

• Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an F grade for the entire course.

• All students are expected to write and debug their codes individually.

• Students are encouraged to help and support each other in all problems related to the – basic understanding of the problem – operation of the CAD tools.