Transcript Lecture #30 Finite State Machines • Last lecture: – CMOS fabrication – Clocked and latched circuits • This lecture: – Finite State Machines 11/10/2004 EE 42 fall.

Lecture #30 Finite State Machines
• Last lecture:
– CMOS fabrication
– Clocked and latched circuits
• This lecture:
– Finite State Machines
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EE 42 fall 2004 lecture 30
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Finite State Machines
• The digital model we are looking at is an implementation
of a finite state machine.
• A FSM has several states, corresponding to the values
of each of the registers. Inputs into the machine are
combined with the current state of the machine to
determine the next state of the machine.
• Most complex digital systems are made from one or
more finite state machines, because they can be more
easily analyzed than asynchronous digital logic
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Block diagram
This is a block
diagram of a
particular
kind of FSM.
(a Mealy
machine with
delayed
outputs)
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outputs
Inputs (N)
Register
(N+M edge
triggered
flip-flops)
Combinatorial
Logic
Clock
Current state of the system: Q(M)
Clock
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Timing diagram for synchronous
FSM
Clock
Inputs
Logic
State
Output
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A computer as a FSM
• A computer could be viewed as a FSM,
• or you could view just the CPU as a FSM,
accesses from the main memory as outputting
addresses, followed by input of data from the
memory, etc.
• A CPU might also be viewed as several
interacting FSMs.
– An accumulator
– A memory interface unit
– An instruction sequencer
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State Transition tables
State
Input
(received 6 Next bit
bits so far)
(received 7 Next bit
bits so far)
Next state
Output
Received 7 none
bits so far
Have
The byte
received
received
byte
It is implicit that transitions occur only at discrete times
(such as clock edges)
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Defining State Machines
Example: Suppose I am playing a game by tossing a coin.
If I toss 3 heads in a row, I win.
If I toss a tail before tossing three heads, I lose.
States = {0_heads, 1_head, 2_heads}
Inputs = {head, tail, absent}
Outputs = {win, lose, absent}
initialState = 0_heads
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Defining State Machines: Table
This state machine can be defined using a table:
(s(n+1), y(n)) = update(s(n), x(n))
x(n) = head
s(n) = 0_heads
s(n) = 1_head
s(n) = 2_heads
x(n) = tail
(1_head, absent) (0_heads, lose)
(2_heads, absent) (0_heads, lose)
(0_heads, lose)
(0_heads, win)
Output absent means that there is no output at this transition
There is a more visually appealing way to define the
update function: a state diagram.
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Defining State Machines: State Diagram
To create a state diagram for a state machine, first draw circles
representing the states.
head / absent
head / absent
tail / lose
0_heads
1_head
2_heads
tail / lose
tail / lose
head / win
For each combination of input and state, draw an arrow from the current
state to the next state.
Label the arrow with the input and output that create the transition as
shown: “input/output”
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State Machines: State Response
The state response is sequence of states resulting from a
particular input sequence.
Example: Find the state response and output sequence for
tail head head
head / absent
x=
tail / lose
0_heads
tail
head / absent
1_head
2_heads
tail / lose
tail / lose
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head / win
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Facts About State Machines
• The state machines addressed here are called Mealy
machines. Mealy machines generate outputs during state
transitions.
• Moore machines generate output while the system is in a
particular state (output depends on state only).
• Each transition and output depends only on the current state
and current input.
• Previous input elements only affect the transitions and output
insofar as they determine the current state.
• A transition will be defined for every possible combination of
input and current state.
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Deterministic vs Nondeterministic
• For the state machines studied in this lecture, there is exactly one
possible transition for each combination of current state and input.
These state machines are called deterministic.
• Sometimes it is useful to model a system using a state machine that
has more than one possible transition for each combination of
current state and input. These state machines are called nondeterministic.
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FSMs in programs
• The finite state machine model can be
useful in the design of software as well as
the design of hardware.
• If a program is responding to external
events, which are not happening in a
controlled order, a FSM description of the
program can describe its high level
operation better than sequential
descriptions.
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Implementing Sequential Logic
• Sequential Circuits
– Simple circuits with feedback
– Latches
– Edge-triggered flip-flops
• Timing Methodologies
– Cascading flip-flops for proper operation
– Clock skew
• Asynchronous Inputs
– Metastability and synchronization
• Basic Registers
– Shift registers
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Sequential Circuits
•
Circuits with Feedback
– Outputs = f(inputs, past inputs, past outputs)
– Basis for building "memory" into logic circuits
• State is memory
• State is an "output" and an "input" to combinational logic
• Combination storage elements are also memory
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Circuits with Feedback
Need to stop values from cycling around
endlessly
X1
X2
•
•
•
Xn
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switching
network
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Z1
Z2
•
•
•
Zn
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Memory with Cross-coupled
Gates
• Cross-coupled NOR gates
– Similar to inverter pair, with capability to force output to 0
(reset=1) or 1 (set=1)
R
Q
S
Q'
Q
R
S
• Cross-coupled NAND gates
– Similar to inverter pair, with capability to force output to 0
(reset=0) or 1 (set=0)
S'
R'
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Q
S'
R'
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Q
Q'
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Timing Behavior
Reset
Hold
R
Q
S
Q'
Set
Reset
Set
100
Race
R
S
Q
\Q
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R-S Latch Analysis
• Break feedback path
R
R
0
0
1
1
0
0
1
1
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Q(t)
0
1
0
1
0
1
0
1
Q(t+)
S
R
Q'
S
S
0
0
0
0
1
1
1
1
Q(t)
Q
Q(t+)
0
hold
1
0 reset
0
1 set
1
X not allowed
X
S
Q(t)
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0
0
X
1
1
0
X
1
R
characteristic equation
Q(t+) = S + R’ Q(t)
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Gated R-S Latch
• Control when R and S
inputs matter
– Otherwise, the
slightest glitch on R or
S while enable is low
could cause
change in value stored
Set
R
R'
Q
enable'
Q'
S'
S
100
Reset
S'
R'
enable'
Q
Q'
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Clocks
• Used to keep time
– Wait long enough for inputs (R' and S') to settle
– Then allow to have effect on value stored
• Clocks are regular periodic signals
– Period (time between ticks)
– Duty-cycle (time clock is high between ticks - expressed as % of
period)
duty cycle (in this case, 50%)
period
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Clocks (cont’d)
• Controlling an R-S latch with a clock
– Can't let R and S change while clock is active (allowing R and S
to pass)
– Only have half of clock period for signal changes to propagate
– Signals must be stable for the other half of clock period
R'
R
Q
clock'
S'
Q'
S
stable changing stable changing stable
R' and S'
clock
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Cascading Latches
• Connect output of one latch to input of another
• How to stop changes from racing through chain?
– Need to control flow of data from one latch to the next
– Advance from one latch per clock period
– Worry about logic between latches (arrows) that is too
fast
R
R
Q'
R
Q'
S
S
Q
S
Q
clock
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Master-Slave Structure
• Break flow by alternating clocks (like an air-lock)
– Use positive clock to latch inputs into one R-S latch
– Use negative clock to change outputs with another R-S latch
• View pair as one basic unit
– master-slave flip-flop
– twice as much logic
– output changes a few gate delays after the falling edge of clock
but does not affect any cascaded flip-flops
slave stage
master stage
CLK
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R
R
Q'
S
S
Q
P'
P
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R
Q'
S
Q
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The Catching Problem
• In first R-S stage of master-slave FF
– 0-1-0 glitch on R or S while clock is high "caught" by master
stage
– Leads to constraints on logic to be hazard-free
slave stage
master stage
Set
S
R
CLK
P
P'
Q
Q'
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Reset
1s
catch
R
R
Q'
S
S
Q
P'
P
R
Q'
S
Q
CLK
Master
Outputs
Slave
Outputs
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D Flip-Flop
• Make S and R complements of each other
– Eliminates catching problem
– Can't just hold previous value (must have new value ready every
clock period)
– Value of D just before clock goes low is what is stored in flip-flop
– Can make R-S flip-flop by adding logic to make D = S + R' Q
slave stage
master stage
D
R
Q'
S
Q
P'
P
CLK
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R
Q'
Q'
S
Q
Q
10 gates
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Edge-Triggered Flip-Flops
• More efficient solution: only 6 gates
– sensitive to inputs only near edge of clock signal (not while high)
D’
D
holds D' when
clock goes low
0
R
Q
Clk=1
Q’
S
negative edge-triggered D
flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time
constraints to successfully
capture input
0
D
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D’
holds D when
clock goes low
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characteristic equation
Q(t+1) = D
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