Transcript IEEE Std P1532 A New Standard for 1149.1-based In System Configuration Neil G.

IEEE Std P1532
A New Standard for 1149.1-based
In System Configuration
Neil G. Jacobson, Chair
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Historical Perspective
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ISP (In System Programming) first
developed in 1993 using proprietary bus
& protocol
Simultaneous demand for boundaryscan and ISP leads to general adoption
of 1149.1 bus & protocol
Similar but different implementations
result in custom tool environment
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Historical Perspective

Inaugural meeting April, 1996
– Attended by semiconductor manufacturers,
tool developers, ATE manufacturers and
system designers
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E-mail reflector established
Meetings held quarterly
Draft developed for review
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Mission
To define, document and promote the use of a
standardized process and methodology for
implementing programming
capabilities…utilizing (and compatible with)
the 1149.1 communication protocol.
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Benefits
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Serve as development model for new devices
Build on existing, well-supported and
understood standard (1149.1, BSDL)
Standardize tool, development system, test
and manufacturing interfaces to provide
“instant” device support
Facilitate innovation and the development of
new application areas
Enable “concurrent programming” capabilities
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P1532 Application Space

It is the intention of P1532 to be
applicable, usable and practical for:
– FPGA’s
– CPLD’s
– PROM’s
I.E., ANY PROGRAMMABLE DEVICE
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Progress so far...
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Description of silicon implementation
requirements completed and
proceeding to ballot.
Description of BSDL extensions
continuing to be filed as a supplement
to the standard.
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1149.1 System Modal States
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System Mode
Test Mode
Any test Instruction
Loaded
Any non-test
instruction loaded
System
Mode
Power
Up
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Any non-test
instruction loaded
Any test instruction
loaded
Test
Mode
Test-Logic-Reset
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P1532 System Modal States
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Unprogrammed Mode
ISC Accessed Mode
ISC Complete Mode
Operational Mode
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P1532 System Modes
Any non-test instruction but
ISC_ENABLE executed
Unprogrammed
(0,0)
ISC_ENABLE executed
TLR and
ISC_Done is clear
t
d
an is se
R
TL one
_D
SC
ISABLE
execute
Power
Up
ISC
Accessed
(1,X)
ISC_D
I
ISC_Done is clear
Any non-test instruction but
ISC_DISABLE executed
d
Test
Mode
ISC_Done is set
Operational
(0,1)
Any non-test instruction but
ISC_ENABLE executed
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E
BL
NA d
E
_
e
ISC xecut
e
An
bu y n o
n
t
an ISC -test
d I _D
SC isa instr
_D ble uct
io
on
e i load n
s c ed
lea
r
Any non-test instruction
but ISC_Disable loaded
and ISC_Done is set
IEEE Std P1532
ISC_DISABLE
loaded
ISC
Complete
(0,X)
Signals:
(ISC_Enabled, ISC_Done)
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P1532 System Modes
ISC
Accessed
Unprogrammed
An
An
yt
y
an non
d n
an IS test
d C_ in
IS E str
C_ na uc
Do ble tio
ne d i n l o
is s cl ad
cle ea ed
ar r
c
tru
s
n
t i ed
es ad
y t lo
Operational
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uc
str
n
i
ed
st
te load
y
n
es
t
loa ins
de tru
d ctio
tio
Test
Mode
n
tio
d
de
l oa t
on s e
cti is
A
u
str led
t in nab
s
-te _E
on ISC
n
d
y
An an
n
ed
ad
l o ar
An
on l e
yt
An
cti is c et
es
u
tr ed s s
t
s
l
i Any test instruction lo ins
n
i
b
e
a
t
a
de truc
n
s n
loaded
d
tio
-te _E _Do
n
n
o SC C
n
I
S
y d dI
n
n
A a an
IEEE Std P1532
ISC
Complete
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P1532 Instruction Set
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Support Basic ISC Functionality
– Concurrent Operations
– Well-defined System Behaviour
• Mandatory Instructions
–
–
–
–
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ISC_ENABLE
ISC_PROGRAM
ISC_DISABLE
ISC_NOOP
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P1532 Instruction Set
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Support Additional Access Mechanisms
–
–
–
–
–
–
–
ISC_DISCHARGE
ISC_SETUP
ISC_PROGRAM_DONE
ISC_ERASE_DONE
ISC_DATA_SHIFT
ISC_ADDRESS_SHIFT
ISC_INCREMENT
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P1532 Memory Model
Basic Structure
Address
Data
Memory Array
(some areas unused)
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P1532 Memory Model
Variation 1
ISC_PData/ISC_RData
TDI
Address
Data
TDO
Memory Array
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P1532 Memory Model
Variation 2
ISC_Address
TDI
ISC_PData/ISC_RData
TDO
Memory Array
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P1532 Memory Model
Variation 3
Address Gen
ISC_Address
TDI
ISC_PData/ISC_RData
TDO
Memory Array
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P1532 Memory Model
Variation 4
Next Address
Control
Address
TDI
ISC_PData/ISC_RData
TDO
Memory Array
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P1532 Memory Model
Variation 5
Address Gen
ISC_Address
TDI
ISC_PData/ISC_RData
TDO
ISC_Config
1 bit
n-1 bits
Non-volatile
Memory Array #1
Addr(n) = 0
Volatile
Memory Array #2
Addr(n) = 1
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P1532 Memory Model
Variation 6
Address Gen
ISC_Address
TDI
ISC_PData/ISC_RData
TDO
Memory Array #1
Addr(n) = 0
Memory Array #2
Addr(n) = 1
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P1532 Instruction Set
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Support Advanced ISC Functionality
–
–
–
–
–
–
ISC_ERASE
ISC_READ
ISC_READ_INFO
ISC_PROGRAM_SECURITY
ISC_PROGRAM_START
ISC_PROGRAM_STOP
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P1532 Optional Status Mechanism
Optional Programming-In-Progress Flag
Optional Status Subcodes
Error Code
N
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2
1
0
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1
0
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P1532 Optional Security Mechanism
ISC_Disable_Read
ISC_Disable_Program
Internal Protection
Control Register
ISC_Disable_Erase
N-Bit Key
All 0's
Transfer of N+3 bits occurs
on the completion of
ISC_PROGRAM_SECURITY
IF (All 0's OR Equal) AND Not All 1's
All 1's
N
Equal
N
TDI
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ISC_PData
IEEE Std P1532
TDO
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P1532 BSDL
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Supported through BSDL EXTENSION
Description sufficient to indicate:
– Device ISC Capabilities
– Allowable Mode Transitions
– Operational Flows
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Joining the Ballot Group
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You must be a member of the IEEE-SA.
You must be committed to reading,
understanding and returning the ballot
document.
Submit your contact information to me now!
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Joining the Working Group
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Meetings are scheduled at least 4
weeks in advance
They are 2 days in length and generally
in the San Jose area
To become a voting member, you must:
– Attend two consecutive meetings.
– Express an interest in joining.
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Information Sources
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Executive Committee
– Neil Jacobson, Chair
• [email protected]
– Dave Bonnett, Vice Chair
• [email protected]
– Ted Eaton, Secretary
• [email protected]
– Ken Parker, Technical Editor
• [email protected]
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Information Sources
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Invitation to Ballot Group
– Contact Neil Jacobson
• [email protected]
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E-mail Reflector
– [email protected]
• Contact Neil Jacobson to join
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Web Page
– http://grouper.ieee.org/groups/1532/index.html
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