Transcript ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL George Mason University.

ECE 448
Lecture 3
Combinational-Circuit Building
Blocks
Data Flow Modeling of
Combinational Logic
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3, RT-level combinational circuit
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 6, Combinational-Circuit Building Blocks
Chapter 5.5, Design of Arithmetic Circuits Using
CAD Tools
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VHDL Design Styles
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VHDL Design Styles
VHDL Design
Styles
• Testbenches
dataflow
Concurrent
statements
structural
Components and
interconnects
behavioral
(sequential)
Sequential statements
• Registers
• State machines
• Instruction decoders
Subset most suitable for synthesis
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Synthesizable VHDL
Dataflow VHDL
Design Style
VHDL code
synthesizable
Dataflow VHDL
Design Style
VHDL code
synthesizable
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Data-Flow VHDL
Concurrent Statements
•
concurrent signal assignment
()
•
conditional concurrent signal assignment
(when-else)
•
selected concurrent signal assignment
(with-select-when)
•
generate scheme for equations
(for-generate)
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Modeling Wires and Buses
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Signals
SIGNAL a : STD_LOGIC;
a
1
wire
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);
b
8
ECE 448 – FPGA and ASIC Design with VHDL
bus
8
Merging wires and buses
a
4
10
b
5
d
c
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a:
b:
c:
d:
STD_LOGIC_VECTOR(3 DOWNTO 0);
STD_LOGIC_VECTOR(4 DOWNTO 0);
STD_LOGIC;
STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;
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Splitting buses
a
4
d
10
5
b
c
SIGNAL
SIGNAL
SIGNAL
SIGNAL
a:
b:
c:
d:
STD_LOGIC_VECTOR(3 DOWNTO 0);
STD_LOGIC_VECTOR(4 DOWNTO 0);
STD_LOGIC;
STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);
b <= d(5 downto 1);
c <= d(0);
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Combinational-Circuit
Building Blocks
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Fixed Shifters & Rotators
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Fixed Shift in VHDL
SIGNAL A :
STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3) A(2) A(1) A(0)
A
A>>1
AshiftR
‘0’
A(3) A(2) A(1)
AshiftR <=
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Fixed Rotation in VHDL
SIGNAL A :
STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3) A(2) A(1) A(0)
A
A<<<1
ArotL
A(2) A(1) A(0) A(3)
ArotL <=
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Gates
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Basic Gates – AND, OR, NOT
x1
x2
x1
x2
x1  x2   xn
x1  x2
xn
(a) AND gates
x1
x2
x1
x2
x1 + x2+ + xn
x1 + x2
xn
(b) OR gates
x
x
(c) NOT gate
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Basic Gates – NAND, NOR
x1
x2
x1
x2
x 1  x 2    x n
x 1  x 2
xn
(a) NAND gates
x1
x1
x2
x2
x 1 + x 2 +  + x n
x1 + x2
xn
(b) NOR gates
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DeMorgan’s Theorem and other symbols
for NAND, NOR
x1
x2
x1
x1
x2
x2
(a)
x1
x2
x1 x2 = x1 + x2
x1
x1
x2
x2
(b)
x1 + x2 = x1 x2
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Basic Gates – XOR
x1 x2
0
0
1
1
0
1
0
1
f = x1 x2
0
1
1
0
(a) Truth table
x1
f = x1 x2
x2
(b) Graphical symbol
x1
x2
f = x1 x2
(c) Sum-of-products implementation
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Basic Gates – XNOR
x1 x2
0
0
1
1
0
1
0
1
f = x1 x2
1
0
0
1
(a) Truth table
x1
f = x1 x2 = x1 . x2
x2
(b) Graphical symbol
x1
x2
f = x1 x2
(c) Sum-of-products implementation
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Data-flow VHDL: Example
x
y
s
cin
cout
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Data-flow VHDL: Example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( x
: IN
y
: IN
cin
: IN
s
: OUT
cout : OUT
END fulladd ;
ECE 448 – FPGA and ASIC Design with VHDL
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
22
Data-flow VHDL: Example (2)
ARCHITECTURE dataflow OF fulladd IS
BEGIN
s
<= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;
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Logic Operators
• Logic operators
and
or
nand
nor
xor
not
• Logic operators precedence
xnor
only in VHDL-93
Highest
and
or
not
nand
nor
xor
xnor
Lowest
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No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
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Multiplexers
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2-to-1 Multiplexer
s
w
0
0
w
1
1
f
(a) Graphical symbol
ECE 448 – FPGA and ASIC Design with VHDL
s
f
0
w
0
1
w
1
(b) Truth table
27
VHDL code for a 2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN
STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;
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Cascade of two multiplexers
w
3
0
w
2
1
0
w
1
y
1
s2
s1
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VHDL code for a cascade of
two multiplexers
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2
: IN STD_LOGIC ;
f
: OUT STD_LOGIC ) ;
END mux_cascade ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGIN
f <= w1 WHEN s1 = ‘1' ELSE
w2 WHEN s2 = ‘1’ ELSE
w3 ;
END dataflow ;
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Operators
• Relational operators
=
/=
<
<=
>
>=
• Logic and relational operators precedence
Highest
Lowest
=
and
/=
or
ECE 448 – FPGA and ASIC Design with VHDL
not
<
<=
nand
nor
>
xor
>=
xnor
31
Priority of logic and relational operators
compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …
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VHDL operators
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4-to-1 Multiplexer
s
0
s
1
w
w
w
w
0
00
1
01
2
10
3
11
(a) Graphic symbol
ECE 448 – FPGA and ASIC Design with VHDL
f
s
1
s
0
f
0
0
w
0
1
w
1
0
w
1
1
w
0
1
2
3
(b) Truth table
34
VHDL code for a 4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3
s
f
END mux4to1 ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END dataflow ;
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Decoders
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2-to-4 Decoder
En w w
1 0
y y y y
3 2 1 0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
1
1
0
0
0
0
x
x
0
0
0
0
(a) Truth table
ECE 448 – FPGA and ASIC Design with VHDL
w
1
w
0
En
y
3
y
2
y
1
y
0
(b) Graphical
symbol
37
VHDL code for a 2-to-4 Decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN
En : IN
y
: OUT
END dec2to4 ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= “0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;
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Adders
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16-bit Unsigned Adder
16
16
X
Y
Cout
Cin
S
16
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Arithmetic Operators in VHDL (1)
To use basic arithmetic operations involving
std_logic_vectors you need to include the
following library packages:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
or
USE ieee.std_logic_signed.all;
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Arithmetic Operators in VHDL (2)
You can use standard + and - operators
to perform addition and subtraction:
signal A :
signal B :
signal C :
……
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
C <= A + B;
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VHDL code for a 16-bit Unsigned Adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY adder16 IS
PORT ( Cin
X, Y
S
Cout
END adder16 ;
: IN
: IN
: OUT
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF adder16 IS
SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
END dataflow ;
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Comparators
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4-bit Number Comparator
4
A
4
AeqB
AgtB
B
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AltB
45
VHDL code for a 4-bit Unsigned Number
Comparator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY compare IS
PORT ( A, B
: IN
AeqB, AgtB, AltB : OUT
END compare ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF compare IS
BEGIN
AeqB <= '1' WHEN A = B ELSE '0' ;
AgtB <= '1' WHEN A > B ELSE '0' ;
AltB <= '1' WHEN A < B ELSE '0' ;
END dataflow ;
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VHDL code for a 4-bit Signed Number
Comparator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY compare IS
PORT ( A, B
: IN
AeqB, AgtB, AltB : OUT
END compare ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF compare IS
BEGIN
AeqB <= '1' WHEN A = B ELSE '0' ;
AgtB <= '1' WHEN A > B ELSE '0' ;
AltB <= '1' WHEN A < B ELSE '0' ;
END dataflow ;
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Buffers
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Tri-state Buffer
e
x
f
e= 0
(a) A tri-state buffer
e x
0
0
1
1
0
1
0
1
x
f
e= 1
f
x
Z
Z
0
1
f
(b) Equivalent circuit
(c) Truth table
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Four types of Tri-state Buffers
e
e
f
x
f
x
(a)
(b)
e
e
f
x
(c)
ECE 448 – FPGA and ASIC Design with VHDL
f
x
(d)
50
Tri-state Buffer – example (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC;
output: OUT STD_LOGIC
);
END tri_state;
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Tri-state Buffer – example (2)
ARCHITECTURE dataflow OF tri_state IS
BEGIN
output <= input WHEN (ena = ‘1’) ELSE ‘Z’;
END dataflow;
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Encoders
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Priority Encoder
w0
y0
w1
y1
w2
z
w3
w3 w2 w1 w0
0
0
0
0
1
0
0
0
1
x
ECE 448 – FPGA and ASIC Design with VHDL
0
0
1
x
x
0
1
x
x
x
y1 y0
z
d
0
0
1
1
0
1
1
1
1
d
0
1
0
1
54
VHDL code for a Priority Encoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN
y : OUT
z : OUT
END priority ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;
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Describing
Combinational Logic
Using
Dataflow Design Style
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MLU Example
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MLU Block Diagram
MUX_0
A
0
A1
MUX_4_1
1
Y1
IN0
NEG_A
MUX_1
MUX_2
IN1
IN2
0
OUTPUT
1
SEL0
IN3
SEL1
NEG_Y
B
0
B1
L1 L0
1
MUX_3
NEG_B
Y
MLU: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A:
IN STD_LOGIC;
B:
IN STD_LOGIC;
L1 :
IN STD_LOGIC;
L0 :
IN STD_LOGIC;
Y:
OUT STD_LOGIC
);
END mlu;
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MLU: Architecture Declarative Section
ARCHITECTURE mlu_dataflow OF mlu IS
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
A1 : STD_LOGIC;
B1 : STD_LOGIC;
Y1 : STD_LOGIC;
MUX_0 : STD_LOGIC;
MUX_1 : STD_LOGIC;
MUX_2 : STD_LOGIC;
MUX_3 : STD_LOGIC;
L: STD_LOGIC_VECTOR(1 DOWNTO 0);
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MLU - Architecture Body
BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE
A;
B1<= NOT B WHEN (NEG_B='1') ELSE
B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;
MUX_0 <= A1
MUX_1 <= A1
MUX_2 <= A1
MUX_3 <= A1
AND B1;
OR B1;
XOR B1;
XNOR B1;
L <= L1 & L0;
with (L) select
Y1 <= MUX_0
MUX_1
MUX_2
MUX_3
WHEN "00",
WHEN "01",
WHEN "10",
WHEN OTHERS;
END mlu_dataflow;
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Logic Implied Most Often by
Conditional and Selected
Concurrent Signal
Assignments
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Data-flow VHDL
Major instructions
Concurrent statements
•
•
•
•
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)
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Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
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Most often implied structure
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
Value N
Value N-1
0
1
.…
…
0
1
0
1
Value 2
Target Signal
Value 1
Condition N-1
Condition 2
Condition 1
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Data-flow VHDL
Major instructions
Concurrent statements
•
•
•
•
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)
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Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
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Most Often Implied Structure
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
expression1
choices_1
expression2
choices_2
target_signal
expressionN
choices_N
choice expression
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Allowed formats of choices_k
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS
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Allowed formats of choice_k - example
WITH sel SELECT
y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;
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