Transcript Lecture #32 Registers, counters etc. • Last lecture: – Digital circuits with feedback – Clocks – Flip-Flops • This Lecture: – Edge triggers – Registers – shift registers –

Lecture #32 Registers, counters etc.
• Last lecture:
– Digital circuits with feedback
– Clocks
– Flip-Flops
• This Lecture:
– Edge triggers
– Registers
– shift registers
– counters
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EE 42 fall 2004 lecture 32
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Edge triggering
• The last lecture ended with how a flip flop
could be designed by using two latches
which cascaded in a master-slave
relationship.
• Another way of creating an edge triggered
flip flop is to use logic with feedback, as in
the following slide.
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Edge-Triggered Flip-Flops
• More efficient solution: only 6 gates
– sensitive to inputs only near edge of clock signal (not while high)
holds D' when
clock goes low
R
Q
Clk=1
S
Q’
holds D when
clock goes low
D
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EE 42 fall 2004 lecture 32
negative edge-triggered D
flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time
constraints to successfully
capture input
characteristic equation
Q(t+1) = D
3
Edge-Triggered Flip-Flops
(cont’d)
• Positive edge-triggered
– Inputs sampled on rising edge; outputs change after rising edge
• Negative edge-triggered flip-flops
– Inputs sampled on falling edge; outputs change after falling edge
100
D
CLK
Qpos
positive edge-triggered FF
Qpos'
Qneg
negative edge-triggered FF
Qneg'
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Timing Methodologies
• As we have seen, there are several different ways
of designing a sequential logic circuit. In general,
each circuit will stick with a set of rules which are
designed to achieve consistently accurate results.
• A set of rules for interconnecting components and
clocks are adopted which will guarantee proper
operation of system when strictly followed.
• Approach depends on building blocks used for
memory elements. Edge-triggered flip-flops are
found in programmable logic devices
• Many custom integrated circuits focus on levelsensitive latches
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• Basic rules for correct timing:
– Inputs to flip-flops are stable and correct for
and interval around the time of sampling
(avoid asynchronous inputs wherever
possible)
– No flip-flop changes state more than once per
clocking event
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Definition: Set up time/hold time
Tsu Th
data
D Q
D Q
input
clock
clock
stable changing
data
clock
To ensure that the data signal is captured
accurately, the data must be stable for an
time tsu (set up) before the edge, and kept
constant for a time th (hold) after the edge.
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Comparison of Latches and
Flip-Flops
D Q
CLK
positive
edge-triggered
flip-flop
D
CLK
Qedge
D Q
G
Qlatch
CLK
transparent
(level-sensitive)
latch
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behavior is the same unless input changes
while the clock is high
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Comparison of Latches and
Flip-Flops (cont’d)
Type
When inputs are sampled When output is valid
unclocked
latch
always
propagation delay from input change
level-sensitive
latch
clock high
(Tsu/Th around falling
edge of clock)
propagation delay from input change
or clock edge (whichever is later)
master-slave
flip-flop
clock high
(Tsu/Th around falling
edge of clock)
propagation delay from falling edge
of clock
negative
clock hi-to-lo transition propagation delay from falling edge
edge-triggered (Tsu/Th around falling
of clock
flip-flop
edge of clock)
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Typical Timing Specifications
• Positive edge-triggered D flip-flop
– Setup and hold times
– Minimum clock width
– Propagation delays
D
CLK
Tsu
Th
0.8 ns0.5 ns
Tsu
Th
0.8 ns 0.5 ns
Tw 1ns
all measurements are made from the clocking event that is,
the rising edge of the clock
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Cascading Edge-triggered Flip-Flops
• Shift register
– New value goes into first stage
– While previous value of first stage goes into second stage
– The propagation time must be longer than the hold time
IN
D Q
Q0
D Q
Q1
OUT
CLK
100
IN
Q0
Q1
CLK
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Cascading Edge-triggered FlipFlops (cont’d)
• Why this works
– Propagation delays exceed hold times
– Clock width constraint exceeds setup time
– This guarantees following stage will latch current value before it
changes to new value
In
Q0
Tsu
4ns
Tsu
4ns
Tp
3ns
Q1
Tp
3ns
assumes infinitely fast
distribution of the clock
CLK
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timing constraints
guarantee proper
operation of
cascaded components
Th
2ns
Th
2ns
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2004 lecture 32
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Clock Skew
• The problem
– Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
– This is difficult in high-performance systems because time for
clock to arrive at flip-flop is comparable to delays through logic
– Effect of skew on cascaded flip-flops:
In
Q0
100
Q1
CLK1 is a delayed
version of CLK0
CLK0
CLK1
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
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Summary of Latches and FlipFlops
• Development of D-Flip-Flop
– Level-sensitive used in custom integrated circuits
• can be made with 4 gates
– Edge-triggered used in programmable logic devices
– Good choice for data storage register
• Historically J-K Flip Flop was popular but now never used
– Similar to R-S but with 1-1 being used to toggle output (complement state)
– Can always be implemented using D-FF
• Preset and clear inputs are highly desirable on flip-flops
– Used at start-up or to reset system to a known state
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Flip-Flop Features
• Reset (set state to 0) – R
– Synchronous: Dnew = R' • Dold (when next clock edge arrives)
– Asynchronous: doesn't wait for clock, quick but dangerous
• Preset or set (set state to 1) – S (or sometimes P)
– Synchronous: Dnew = Dold + S (when next clock edge arrives)
– Asynchronous: doesn't wait for clock, quick but dangerous
• Both reset and preset
– Dnew = R' • Dold + S (set-dominant)
– Dnew = R' • Dold + R'S
(reset-dominant)
• Selective input capability (input enable/load) – LD or EN
– Multiplexer at input: Dnew = LD' • Q + LD • Dold
– Load may/may not override reset/set (usually R/S have priority)
• Complementary outputs – Q and Q'
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Registers
• Collections of flip-flops with similar controls and logic
– Stored values somehow related (e.g., form binary value)
– Share clock, reset, and set lines
– Similar logic at each stage
• Examples
– Shift registers
– Counters
"0"
OUT1
OUT2
R S
D Q
OUT3
R S
D Q
R S
D Q
OUT4
R S
D Q
CLK
IN1
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IN2
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IN3
IN4
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Shift Register
• Holds samples of input
– Store last 4 input values in sequence
– 4-bit shift register:
OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
OUT4
D Q
CLK
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Shift Register Application
• Parallel-to-serial conversion for serial
transmission
parallel outputs
parallel inputs
serial transmission
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Pattern Recognizer
• Combinational function of input samples
– In this case, recognizing the pattern 1001 on
the single input signal
OUT
OUT1
IN
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
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Binary Counter
• Logic between registers (not just multiplexer)
– XOR decides when bit should be toggled
– Always for low-order bit, only when first bit is true for
second bit, and so on
OUT1
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
"1"
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Sequential Logic Summary
• Fundamental building block of circuits with state
– R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
– Latch and flip-flop
• Timing methodologies
– Use of clocks
– Cascaded FFs work because prop delays exceed hold times
– Beware of clock skew
• Asynchronous inputs and their dangers
– Synchronizer failure: what it is and how to minimize its impact
• Basic registers
– Shift registers
– Pattern detectors
– Counters
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