Transcript ECE 5465 Thumb Instruction Set Single/Multiple register data transfer instruction Outline ● Introduction to thumb instruction set (He Liu) ● Thumb single register data.

ECE 5465 Thumb
Instruction Set
Single/Multiple register data transfer instruction
Outline
● Introduction to thumb instruction set (He Liu)
● Thumb single register data transfer
instructions (Hongtao Xia)
● Thumb mutiple register data transfer
instructions (Shengheng Zhang)
Outline
● Introduction to thumb instruction set (He
Liu)
● Thumb single register data transfer
instructions (Hongtao Xia)
● Thumb mutiple register data transfer
instructions (Shengheng Zhang)
Thumb bit in the CPSR
● Bit 5 of the CPSR
If T is set, the instruction stream is interpreted as
a 16-bit Thumb instruction.
o otherwise, -> standard ARM instructions.
o
Entery Thumb
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Bit[0] of Rm is copied into the T bit in the CPSR and bits[31:1] are moved into the PC:
If Rm[0] is 1, the processor switches to execute Thumb instructions and begins executing at the address in
Rm aligned to a half-word boundary by clearing the bottom bit.
If Rm[0] is 0, the processor continues executing ARM instructions and begins executing at the address in
Rm aligned to a word boundary by clearing Rm[l].
Call Thumb
Thumb System
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Full access to the eight 'Lo' general purpose registers r0 to r7
r13 is used as a stack pointer.
r14 is used as the link register.
r15 is the program counter (PC).
r8 to r12 and the CPSR have only restricted access
Thumb&ARM
Most Thumb instructions are executed unconditionally.
(All ARM instructions are executed conditionally.)
• Many Thumb data processing instructions use a 2-address format (the destination
register is the same as one of the source registers).
(ARM data processing instructions, with the exception of the 64-bit multiplies,
use a 3-address format.)
• Thumb instruction formats are less regular than ARM instruction formats, as a
result of the dense encoding.
Outline
● Introduction to thumb instruction set (He Liu)
● Thumb single register data transfer
instructions (Hongtao Xia)
● Thumb mutiple register data transfer
instructions (Shengheng Zhang)
Single Register Data transfer instructions
Binary Encoding:
(1)Load/Store with immediate offset
Example
(2)Load/store halfword
Example
(3)Load/Store sign-extended byte/halfword
Example
(4)PC-relative Load
Example
(5)SP-relative Load/Store
Example
(6)Load/Store with register offset
Example
(7)Load Address
(8)Add Offset to Stack Pointer
Outline
● Introduction to thumb instruction set (He Liu)
● Thumb single register data transfer
instructions (Hongtao Xia)
● Thumb mutiple register data transfer
instructions (Shengheng Zhang)
Thumb mutiple register data transfer instructions
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reg list- any of the ‘Lo’ registers (r0-r7)
Stack instruction- SP(r13), always use write-back
Push instrcution- LR(r14)
POP instrcution- PC(r15)
Multiple load/store
Example:
STMIA R9!, {R0,R1,R5} ; store the contents of registers R0,R1,R5 starting at
the address specfied in R0, incremening the
addresses R9 for each word
; write back the update value of R9
Push/Pop registers
Example:
PUSH {R0-R4, LR}
POP {R2, R6, PC}
; Store R0, R1, R2, R3 ,R4 and R14(LR) at the stack
pointed to by R13(SP) and update R13
; Useful at start of a sub-routine to save workspace and
return address
; Load R2, R6 and R15(PC) from the stack pointed to by
R13(SP) and update R13
; Useful to restore workspace and return from
sub-routine
References
[1] ARMv7-M Architecture Reference Manual
[2] ARM system-on-chip architecture, second edition, Steve Furber, Addison Wesley,
2000.