Transcript CS184a: Computer Architecture (Structure and Organization) Day 6: January 19, 2005 VLSI Scaling Caltech CS184 Winter2005 -- DeHon.

CS184a:
Computer Architecture
(Structure and Organization)
Day 6: January 19, 2005
VLSI Scaling
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Caltech CS184 Winter2005 -- DeHon
Today
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VLSI Scaling Rules
Effects
Historical/predicted scaling
Variations (cheating)
Limits
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Why Care?
• In this game, we must be able to predict
the future
• Rapid technology advance
• Reason about changes and trends
• re-evaluate prior solutions given
technology at time X.
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Why Care
• Cannot compare against what
competitor does today
– but what they can do at time you can ship
• Careful not to fall off curve
– lose out to someone who can stay on
curve
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Scaling
• Premise: features scale “uniformly”
– everything gets better in a predictable
manner
• Parameters:
 l (lambda) -- Mead and Conway (class)
 S -- Bohr
 1/k -- Dennard
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Feature Size
l is half the minimum
feature size in a VLSI
process
[minimum feature
usually channel width]
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Scaling
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Channel Length (L)
Channel Width (W)
Oxide Thickness (Tox)
Doping (Na)
Voltage (V)
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Scaling
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•
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Channel Length (L)
l
Channel Width (W)
l
Oxide Thickness (Tox) l
Doping (Na)
1/l
Voltage (V)
l
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Effects?
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Area
Capacitance
Resistance
Threshold (Vth)
Current (Id)
Gate Delay (tgd)
Wire Delay (twire)
Power
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Area
 l  l/k
 A=L*W
 A  A/k2
 130nm  90nm
 50% area
 2x capacity same
area
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Area Perspective
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Capacity Scaling from Intel
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Capacitance
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox Tox/k
– Cox  k Cox
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Capacitance
• Gate Capacitance
 Cgate= A*Cox
 A  A/k2
 Cox  k Cox
 Cgate  Cgate /k
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Threshold Voltage
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Threshold Voltage
• VTH VTH /k
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Current
• Saturation Current
Id=(mCOX/2)(W/L)(Vgs-VTH)2
Vgs=V V /k
VTH VTH /k
W W/k
L L/k
Cox  k Cox
Id Id/k
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Gate Delay
 tgd=Q/I=(CV)/I
 V V /k
 Id  Id/k
 C  C /k
 tgd  tgd /k
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Resistance
• R=rL/(W*t)
• W W/k
• L, t similar
• RkR
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Wire Delay
 twire=RC
 R -> k R
 C -> C /k
 twire -> twire
• …assuming (logical)
wire lengths remain
constant...
• Assume short wire or
buffered wire
• (unbuffered wire
ultimately scales as
length squared)
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Power Dissipation (Static Load)
• Resistive Power
– P=V*I
– V V /k
– Id Id/k
– P P /k2
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Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
 P=(1/2)CV2f
 V V /k
 C  C /k
 P P/k3
• Increase
Frequency?
 tgd  tgd /k
 So: f  kf ?
 P  P/k2
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Effects?
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Area
1/k2
Capacitance
1/k
Resistance
k
Threshold (Vth)
1/k
Current (Id)
1/k
Gate Delay (tgd) 1/k
Wire Delay (twire) 1
Power
1/k2 1/k3
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ITRS Roadmap
• Semiconductor Industry rides this
scaling curve
• Try to predict where industry going
– (requirements…self fulfilling prophecy)
• http://public.itrs.net
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MOS Transistor Scaling
(1974 to present)
S=0.7
[0.5x per 2 nodes]
Pitch
Source: 2001 ITRS - Exec. Summary, ORTC Figure
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Gate
[from Andrew Kahng]
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Half Pitch (= Pitch/2) Definition
Metal
Pitch
(Typical
DRAM)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
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Poly
Pitch
(Typical
MPU/ASIC)
[from Andrew Kahng]
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Node Cycle Time:
0.7x
0.7x
Log Half-Pitch
Scaling Calculator +
1994 NTRS .7x/3yrs
Actual .7x/2yrs
Linear Time
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
N
N+1
Node Cycle Time
(T yrs):
N+2
*CARR(T) =
[(0.5)^(1/2T yrs)] - 1
* CARR(T) = Compound Annual
Reduction Rate
(@ cycle time period, T)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Caltech CS184 Winter2005 -- DeHon
CARR(3 yrs) = -10.9%
CARR(2 yrs) = -15.9%
[from Andrew Kahng]
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ITRS Roadmap Acceleration Continues…Gate Length
Technology Node - DRAM Half-Pitch (nm)
1000
2001 MPU Printed Gate Length
2001 MPU Physical Gate Length
1999 ITRS MPU
Gate-Length
100
2-year
Cycle
3-year
Cycle
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1995
1998
2001
2004
2007
2010
2013
2016
Year of Production
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Caltech CS184 Winter2005 -- DeHon
[from Andrew Kahng]
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ITRS 2003 Gate/Wire Scaling
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What happens to delays?
• If delays in gates/switching?
• If delays in interconnect?
• Logical interconnect lengths?
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Delays?
• If delays in gates/switching?
– Delay reduce with 1/k [l]
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Delays
• Logical capacities growing
• Wirelengths?
– No locallity: Lk
– Rent’s Rule
• L  n(p-0.5)
• [p>0.5]
(slower!)
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Compute Density
• Density = compute / (Area * Time)
 k3>compute density scaling>k
 k3: gates dominate, p<0.5
 k2: moderate p, good fraction of gate delay
– [p from Rent’s Rule again – more on Day12]
 k : large p (wires dominate area and delay)
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Power Density
• P-> P /k2 (static, or increase frequency)
• P-> P/k3 (dynamic, same freq.)
• A -> A/k2
• P/A  P/A … or … P/kA
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Cheating…
• Don’t like some of the implications
– High resistance wires
– Higher capacitance
– Quantum tunnelling
– Need for more wiring
– Not scale speed fast enough
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Improving Resistance
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•
•
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R=rL/(W*t)
W W/k
L, t similar
RkR
Don’t scale t quite as fast.
Decrease r (copper)
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Capacitance and Leakage
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox Tox/k
– Cox  k Cox
Reduce Dielectric Constant e (interconnect)
or Substitute for scaling Tox (gate quantum tunneling)
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Threshold Voltage
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ITRS 2003
Table 81a
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High-K dielectric Survey
Wong/IBM J. of R&D, V46N2/3P133--168
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Wire Layers = More Wiring
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Typical chip cross-section illustrating
hierarchical scaling methodology
Wire
Global (up to 5)
Via
Passivation
Dielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor with
Barrier/Nucleation Layer
Intermediate (up to 4)
Local (2)
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Pre Metal Dielectric
Tungsten Contact Plug
[from Andrew Kahng]
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Improving Gate Delay
 tgd=Q/I=(CV)/I
 V V /k
 Id=(mCOX/2)(W/L)(Vgs-VTH)2
 Id  Id/k
 C  C /k
 tgd  tgd /k
Lower C.
Don’t scale V.
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Don’t scale V:
VV
IkI
tgd  tgd /k2
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…But
Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
 P=(1/2)CV2f
 V V /k
 C  C /k
 P P/k3
• Increase
Frequency?
 f  kf ?
 P  P/k2
If not scale V, power dissipation not scale.
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…And
Power Density
• P P (increase frequency)
• P> P/k (dynamic, same freq.)
 A  A/k2
• P/A  kP/A … or … k2P/A
• Power Density Increases
…this is where some companies have gotten into trouble…
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Physical Limits
• Doping?
• Features?
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Physical Limits
• Depended on
– bulk effects
• doping
• current (many electrons)
• mean free path in conductor
– localized to conductors
• Eventually
– single electrons, atoms
– distances close enough to allow tunneling
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What Is A “Red Brick” ?
• Red Brick = ITRS Technology Requirement with
no known solution
• Alternate definition: Red Brick = something
that REQUIRES billions of dollars in R&D
investment
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[from Andrew Kahng]
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The “Red Brick Wall” - 2001 ITRS vs 1999
Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876
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[from Andrew Kahng]
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Conventional Scaling
• Ends in your lifetime
• …perhaps in your first few years after
grad school…
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Finishing Up...
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Big Ideas
[MSB Ideas]
• Moderately predictable VLSI Scaling
– unprecedented capacities/capability growth
for engineered systems
– change
– be prepared to exploit
– account for in comparing across time
– …but not for much longer
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Big Ideas
[MSB-1 Ideas]
• Uniform scaling reasonably accurate for
past couple of decades
• Area increase k2
– Real capacity maybe a little less?
• Gate delay decreases (1/k)
• Wire delay not decrease, maybe increase
• Overall delay decrease less than (1/k)
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