TEAM “EPA” ELECTRONIC PIN ART Preliminary Design Review Spring 2006 Jonathan Persinger Jonathan Snyder Henry Au-Yeung Devon Dallmann Khushboo Verma.

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Transcript TEAM “EPA” ELECTRONIC PIN ART Preliminary Design Review Spring 2006 Jonathan Persinger Jonathan Snyder Henry Au-Yeung Devon Dallmann Khushboo Verma.

TEAM “EPA” ELECTRONIC PIN ART Preliminary Design Review Spring 2006

Jonathan Persinger Jonathan Snyder Henry Au-Yeung Devon Dallmann Khushboo Verma

Project Description

• An array of pins to display a variety of 3-D images such as: – Pictures – Drawing – Text/Braille – Movies – Games – Integration with topography software (i.e. Google Earth)

Implementation

• Solenoid actuation – PWM Control – 256pin Resolution • Software Algorithms and Programming – Image Processing – Embedded Interface communications • Electronic Hardware – Solenoid controller/selection – Compact Flash interface – External Memory – Power regulation

Power Requirements

• Each Solenoid requires a maximum of 400mA to set. (~1-2W) • Maximum Current will occur at column reset where 16 solenoids will be activated at once => 16 x 0.400A x 5V=32watts • Several voltage rails will be needed to run the logic cores and solenoids.

System Overview

Fallback • Braille/Text • LEDs • Total Grid Reset • Image Processing in MATLAB • Hand Reset • 4x4 Matrix

Goals

      Goals 16x16 pin matrix 4 Levels of pin height Static images Single pic in memory One column reset resolution Joystick drawing      Extra Moving pictures Joystick gaming LCD/picture menu USB transceiver DSP filters

Processor

TMS470R1A256 •32-bit ARM7TDMI core (industrial applications) •64 KB to 1MB flash memory •12 KB static ram •Clock speed up to 24 MHz •14 High-resolution I/O channels •I2C/SPI capable

CPLD Requirements

• Clock Standard bus interface (IIC, SPI, etc.) – SPI allows for full duplex and any length instructions • Counters and/or timers are critical for pin height resolutions. – CPLDs offers consistent delays.

• Pin for pin compatibility with a CPLD with more Function blocks • 4 function blocks • 21 GPIOs • One function block must have at least 16 Macrocells & 16 I/Os.

• +5v tolerance for compatibility with hardware logic and drivers.

ERROR W/ Inst#

CPLD Design

uProc 4 SPI State machine Instruction Packet 19 Decoder Increment Instruction Parity 8bit Inst# Error Checking 3bit Z 4bit X 2bit OP Timer Decoder Logic Gates (ANDs ORs etc.) Inst# | Row 16b | inc Clmn | RST Clmn | PWM | HW-Busy

Driver Circuit Objectives:

• Control of 256 individual solenoids • Minimal part count per pin (cost control!) • Must have the ability to switch polarity on Solenoids • EMI / ESD / EMF suppression & protection • Critical Routing, isolation of current carrying grounds and signal grounds • Design in manual control and circuit isolation for easier debugging.

Proof of Concept: Pin Selection

Proof of Concept:

Solenoid Physics

F

 

N

2

I

2

SB mag

2

L

2  

L R

 

L R

Solenoid Physics

• Pulse duration controls height • Trade offs: larger N, less current needed, larger L, larger time constant

Image Processing

• Process BMP, JPEG images • Use MATLAB for image processing – Obtain color matrix – Algorithm to calculate height of the pin – Obtain x and y location for each pixel along with the height • Store post-processed image to Compact flash • Compile the image to MSP470 assembly • Communicate between CPLD and Microprocessor via Standard Peripheral/Bus Interface • Read information from compact flash – Determine memory mapping to locate pictures on card

CPLD Verilog

• State machine to fix PWM & frequency • Translation of post-processed image to one column at a time versus PWM Duration • Miscellaneous Logic – Pin reset – Column select – Multiplexing/Decoding

Division of Labor

• Henry—

Power management; PCB layout; mechanical design

• Khushboo—

Image processing

• Jonathan S.—

Solenoid control; System integration

• Devon—

Solenoid design; programming

• Jon P—

Programming; PCB layout

Gantt Chart

Parts/Costs

PCB 1st and 2nd run Projected Costs Item cost Total cost $100/run Processor/Programmer Misc. Electronics $200.00

$200.00

$100.00

Pin Rig Solenoids w/ pins Power Supply Materials Spartan III FPGA Misc. Hardware Connectors

TOTAL

0.30/pin $200.00

$300.00

$100.00

$100.00

$100.00

$50.00

$1,350.00

Risks

• Processor/CPLD implementation – Prior experience limited – IC Communication problems • SPI integration complexity • Flash memory access (proprietary?) • Cost/Availability – Manufactured solenoids: Cost? Turn around? Many parts are multiplied by 256 (runaway costs). Coil and pin manufacture as of now is difficult. • Coils – High switched currents could cause re-triggering – Pin height tolerance (all or nothing could result) • Mechanical – Tolerance of solenoid diameter and Rig spacing – Longevity of moving parts

Marketability

• Visually impaired via. Braille coding • Novelty item—place on mantel with wave motion for relaxation • USGS/Boy scout elevation profiles • Automated tattooer • Back massager

Questions & Comments ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?