EPA

Jon Persinger Jonathan Snyder Devon Dallmann Henry Au-Yeung Khushboo Verma

12V 3.3V

Hardware System diagram

3.3V

Power Regulation

1.8V

5V 5V, 10A peak Hardware Debug Compact Flash TMS4 70R1 A256

256k Flash 12k RAM

Get pic button

Pin ready interrupt

CPLD

Send data via SPI

State Machine

17 control lines

Driver Circuit

4x4 Test

16x16 Solenoid Array

Compact Flash

•Non-proprietary •Has built-in controller •Operation in PC Card Memory Mode; FAT16 format •Operates in 16-bit mode

Processor

•Operates 24 MHz •256K on-chip Flash (image processing requires lots of space) •12k on-chip RAM •Use of Rowley CrossWorks and CrossConnect for programming and compiler •Olimex Dev Board •Open source code available for ARM7 architecture •Use of two High End Timers (HET) for PWMs •Built in SPI controller •Provides enough IO for Compact Flash communication in 16-bit mode

Controls Schematic

Driver

•Verification of Driver circuit shown during PDR was completed successfully.

•The addition of a dead time circuit was necessary in order to prevent the reverse current circuit from shorting the supply rails.

•The layout of this circuit is shown here.

CLMN Select CKT CPLD Reverse Current CKT Solenoid

Drive Schematic

PCB Layout

•The PCB is a 4-layer 6.5” x 6.5” board with 2oz copper on signal layers and 1oz on internal layers.

•Logic and current carrying grounds are isolated via a split ground plane.

•Power planes are split to limit the current loops to the drive circuit per row.

•A temporary hardware debug section including manual switches to control a 4x4 binary grid without the processor and CPLD. •High current traces were routed with copper pours and planes to allow for low voltage drops.

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2.

3.

FPGA vs CPLD

CONS

CPLDs do not have to be reprogrammed at every power up (they are static memory not dynamic, a FPGA is programmed and loses its memory when the power goes off). So we'd have to add some sort of PROM (which Xilinx does sell and it's pretty cheap) to program a FPGA at every power on FPGAs are only 2.5 and 3.3 volt compatible, not 5 volt, so we'd have to use step up and step down converters. CPLD is 5 volt compatible 9500 series CPLDs hold their data for at least 20 years, and reprogramable 10,000 times 1.

2.

3.

4.

PROS

CPLDs cost more than FPGAs (cheapest Spartan III is $10 and has more gates in it than the 95288, which is $50) and have less gate space CPLDs have ALOT worse timings than FPGAs, their setup and hold times are a lot longer, the gate delay is longer, the pin to pin delay is longer (all by about a magnitude of at least 10) FPGAs typically come in smaller packages than CPLDs In a CPLD programming is restricted to function blocks and macro cells, in an FPGA it is not (layout is more efficient in an FPGA)

FPGA Simulation/Timing Diagram

RMS



I pk Duty

 500

mA

3 0 .

5  225

mA

3

Solenoids

•1000 turns allows for 5v operation which will yield an RMS current of 225mA with a peak current of 500mA as shown here •The solenoids are constructed with 30AWG copper with a standard enamel coating •The inside diameter is 0.08inches with an outer diameter of 1/4inch •MagneLab will construct 256 coils at a cost of $500 USD.

•Essentially no coil temperature increase, even if left on.

Image Processing and Code

• • • • • Use C++ for Image Processing instead of MATLAB Cimg.h image processing library/Imagemagik (JPEG images) • • • • • Algorithm for Code Load BMP, JPG, PNG images etc Obtain color map for the image Scale the image Use formula to calculate the intensity of each pixel Translate intensity level evenly for the required height levels for the pins • Obtain the x and y values for each pixel and store these along with the corresponding pin heights Code currently loads a BMP image and plots the intensity for • the pixels Compiled executable code size 800KB--Too Big! • Customize Cimg.h, discard unused functions Compile the C++ code using CrossWorks ARM7 Compiler to convert it into Assembly

Power

•120VAC/12VDC, 60W Adapter •Step down converters (12V/5,3.3,1.8V) •5V rail needs to supply 10A (50W) (Buck regulator) •3.3V can source up to 1.5A (Buck regulator) •1.8V rail (LDO regulator), external cap ESR is critical

Responsibilities

•PCB—Jonathan •CPLD/Verilog—Devon •Processor—Jon, Henry •Board Population—Henry, Jonathan •Image Processing—Khushboo, Jon •Solenoid Housing—Jonathan •Documentation—Everyone •Driver Circuit—Jonathan, Henry

Milestones

Milestone I: 1 st pcb board assembled and debugged; hardware able to display image via switches; ability to read from Compact Flash Milestone II: 2 nd pcb board assembled and debugged; processor/code will be stand alone; first draft of user’s manual; majority of technical reference completed Expo: Processor reading images from Compact Flash, formats it, and sends to CPLD; possible extras

Costs

Total project budget: EEF Request: Outside funding: UROP 24 Test Solenoids Use of CNC machine in ITLL $1617.69

Item

4 Layer PCB Revisions 1 and 2 Perf. Board Processor (x4) Development Kit Custom Solenoids (x256) Magnets (x550) Compact flash Card 128mb Power adapter 5V,12A Components for buck regulator Power Supply and control circuitry $200 Amount $900 $75 FREE

Total Cost

$200 $20 $57.64

$399 $500 $50 $15.90

$36.96

Pin Rig – Plastic Pin Rig – Plywood Pin Rig – Foam Pad Pin Rig - Plexiglass Pin Rig – Nuts/Bolts/Spacers Shipping Costs, misc. and taxes

Total:

$30.28

$7.49

$3.49

$1.00

$10 $50

$1617.69

$900

Part Number

N/A 8.5”x8.5” TMS470R1A256 TMDS-FET470R1B1M Made by: Magnelab, Inc Neodymium Iron Boron CF128 (Kingston) DTS120500U N/A 8lb High Density Polyethylene 3/8” x 2” x 4” 1’ x 4.5’ 6.5”x6.5” N/A

Risks

•Processor Issues •Acquired compiler/assembler/programmer this week •Very limited software support •On chip flash hard to work with •Power converters/regulators •Code Optimization •Image processing may not fit into on-chip FLASH •Magnetic Problems •Increase solenoid spacing or •Downsize 8x8 Array

Questions