Transcript Unit 3. Memory - Sinclair Community College

EET 252 Unit 3
Memory
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Read Floyd, Chapter 10.
Study Unit 3 e-Lesson.
Do Lab #3.
Homework #3 and Lab #3 due next
week.
Quiz next week.
Terms for Units of Data
•Bit: The smallest unit of digital data, a single 1
or 0.
•Byte: A group of 8 bits.
•Nibble: A “half-byte”: a group of 4 bits.
•Word: Used in two ways:
•Sometimes means 2 bytes (or 16 bits).
•Sometimes means the data width that a
particular chip or system uses: could be 4
bits, 8 bits, 16 bits, 32 bits, etc.
Kilo-, Mega-, Giga•In engineering notation,
•Kilo means 1,000 (the same as 103)
•Mega means 1,000,000 (same as 106)
•Giga means 1,000,000,000 (same as 109)
•When talking about memories, theses terms have
slightly different meanings:
•Kilo means 1,024 (the same as 210)
•Mega means 1,048,576 (same as 220)
•Giga means 1,073,741,824 (same as 230)
Making Sense of Windows File
Sizes
•Have you ever noticed that when you use
Windows to look at a file’s size, it gives two
numbers that don’t seem to match each other?
•Example: “Size on disk: 624 KB (638,976 bytes)”
•That’s because 624 x 1024 = 638,976.
•How many megabytes (MB) is in a file that
contains 28,311,552 bytes?
Memory Units
The location of a unit of data in a memory is called the
address. In personal computer memories, a byte is the
smallest unit of data that can be addressed.
For example the blue byte is located in address 6.
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Computer Busses
•A computer system has two primary busses:
•The data bus, which carries data and instructions
from one part of the system to another.
•The address bus, which carries addresses of
memory locations or external devices.
•These two busses may have the same width
(number of bits), but they need not.
•When people talk about a “32-bit system” or a “64bit system,” they’re talking about the width of the
data bus.
Write Operations
The two main memory operations are called read and
write. A simplified write operation is shown in which new
data overwrites the original data. Data moves to the
Address register
Data register
memory.
1 0 1
1 0 0 0 1 1 0
Address decoder
1
Address bus
1. The address is placed on the
address bus.
2. Data is placed on the data
bus.
3. A write command is issued.
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1
Byte organized memory array
0
1
0
1
0
1
1
1
1
1
0
0
1
0
1
0
0
1
2
1
0
0
0
0
0
0
1
3
1
1
1
1
1
1
0
0
4
0
0
0
0
0
1
1
0
5
1
0
0
0
1
1
0
1
6
1
1
1
1
1
1
1
1
7
0
0
0
0
1
1
1
1
2
Data bus
3
Write
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Read Operations
The read operation is actually a “copy” operation, as the
original data is not changed. The data bus is a “two-way”
path; data moves from the memory during a read operation.
Address register
Data register
0 1 1
1 1 0 0 0 0 0 1
Address decoder
1
Address bus
1. The address is placed on the
address bus.
2. A read command is issued.
3. A copy of the data is placed
in the data bus and shifted
into the data register.
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Byte organized memory array
0
1
0
1
0
1
1
1
1
1
0
0
1
0
1
0
0
1
2
1
0
0
0
0
0
0
1
3
1
1
0
0
0
0
0
1
4
0
0
0
0
0
1
1
0
5
1
0
0
0
1
1
0
1
6
1
1
1
1
1
1
1
1
7
0
0
0
0
1
1
1
1
3
Data bus
2
Read
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Common Address Bus
Widths
•The width (in bits) of an address bus determines the
number of locations it can address:
Width of Address Bus
Number of locations
8 bits
256
10 bits
1k
16 bits
64 k
20 bits
1M
24 bits
16 M
32 bits
4G
Powers of 2 (from Floyd, p. 809)
•This table answers the following
questions:
1. How many rows are there
in a truth table with n input
variables?
2. What is the MOD of an nbit counter?
3. How many addressable
locations in a memory with
n address pins?
Computer Memory
•A computer’s memory consists of many
memory chips, which may be organized in
different ways.
•Example: in the tiny memory below, each
byte may be contained on a single chip, or
may be spread across two or more chips.
Designating a Memory Chip’s Size
& Layout
•The size and organization of a memory chip is given
by a designation such as 16 x 4.
•The first number (16 in our example) tells how many
addressable locations the chip contains.
•The second number (4 in our example) tells how many
bits are contained in each of these addressable
locations.
•Thus, an 8 x 8 chip, a 16 x 4 chip, and a 64 x 1 chip all
have a bit capacity of 64 bits, but they’re organized
differently.
Address Input Pins
•We can tell how many address pins a memory
chip needs by looking at the first number in its
designation.
•For example, a 16 x 4 chip has 16 addressable
locations. How many address pins are needed if
we want to be able to select any one of these 16
locations?
•How many address pins would an 8 x 8 chip
need?
•How many address pins would a 64 x 1 chip
need?
Data Output Pins
•We can tell how many data output pins a
memory chip needs by looking at the second
number in its designation.
•For example, on a 16 x 4 chip, each location
contains 4 bits, so to read out the contents of any
location, we need 4 data output pins.
•How many data output pins would an 8 x 8 chip
need?
•How many data output pins would a 64 x 1 chip
need?
Data Input Pins?
•Some memory chips are read-only memories
(ROMs). These chips don’t have data input
pins because you cannot change the contents
of the memory locations.
•Other memory chips are read-write memories
(confusingly called RAMs, for “random-access
memory”). These may have data input pins that
are separate from the data output pins, or the
pins may be combined as data input/output
(I/O) pins.
Some Memory Chip Datasheets
•7489 RAM (16 x 4)
•6116 RAM (2048 x 8)
•TMS4700 ROM (1024 x 8)
Memory Addressing
In addition to the address bus and data bus, semiconductor
memories have read and write control signals and chip
select signals. Depending on the type of memory, other
signals may be required.
Read Enable (RE) and Write Enable (WE) signals are sent from the
CPU to memory to control data transfer to or from memory.
Chip Select (CS) or Chip Enable (CE) is used as part of address
decoding. All other inputs are ignored if the Chip Select is not active.
Output Enable (OE) is active during a read operation, otherwise it
is inactive. It connects the memory to the data bus.
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Memory Expansion
Memory can be expanded in either word size or word
capacity or both.
To expand word size:
Notice that the data bus
size is larger, but the
number of address is
the same.
RAM 2m ´ 2n
m bits
m bits
RAM 1
2m ´ n
m bits
D
Data
in/out
RAM 2
2m ´ n
D
Address
bus
n bits
Data
in/out
n bits
Control
bus
2n bits
Data bus
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Memory Expansion
To expand word capacity, Address
you need to add an address 21 bus
bits
line as shown in this example
RAM 2M ´ 8
RAM 1
1M ´ 8
EN
20 bits
8 bits
Control
bus
Notice that the data bus size does
not change.
8 bits Data
bus
20 bits
RAM 2
1M ´ 8
EN
8 bits
What is the purpose of the inverter?
Only one of the ICs is enabled at any time depending on
the logic on the added address line.
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Computer Memory
•A computer’s memory consists of many
memory chips.
•Some of the bits on the address bus are used
to select one of these chips (and to de-select
all of the others).
•The remaining bits on the address bus are
used to select a memory location within the
selected chip….
Computer Memory (Continued)
•Example: Suppose a computer’s memory consists
of 32 memory chips, each of which is 2048 x 8.
•How many bytes does the computer’s memory
contain?
•How many bits are needed to select one of the 32
memory chips?
•Once a chip has been selected, how many bits
are needed to select a memory location within that
chip?
•How wide does this system’s address bus need to
be?
Cache Memory
•A computer system typically has one or more
small, high-speed cache memories in addition to
its large, slower main memory.
•Recently used data and instructions are
temporarily stored in the cache memory so that if
the processor needs them again, they can be
retrieved more quickly than if they had to be
retrieved from the main memory.
•See textbook’s Figure 10.15 (next slide).
Figure 10.15 Block diagram showing L1 and L2 cache memories in a computer system.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Memory Technologies
•Most memory chips fall into one of the following
three categories (which have many subcategories).
1. RAM (Random Access Memory)
•Read/write
•Volatile (Loses data when power is removed.)
2. ROM (Read-Only Memory)
•Impossible or difficult to write to
•Non-volatile
3. Flash memory
•Read/write
•Non-volatile
Random Access Memory (RAM)
•RAM is for temporary data storage. It is read/write memory
and can store data only when power is applied, hence it is
volatile. Two major categories are static RAM (SRAM) and
dynamic RAM (DRAM).
•The memory cells in SRAM are latches or flip-flops.
•The memory cells in Dynamic RAMs (DRAMs) are
capacitors. Since the capacitors lose charge, they must be
refreshed many times each second.
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Figure 10.7 The RAM family.
Latch or flip-flop
storage cell.
Capacitor storage cell.
Must be refreshed.
Fast but lowdensity. Used for
cache memory.
High-density but
slow. Used for
main memory.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Read-Only Memory (ROM)
•Members of the ROM family are all considered nonvolatile, because they retain data with power removed.
•Various members can be either permanent memory (truly
read-only) or erasable (not truly read-only, but they are
difficult to write to).
•ROMs are used to store data that is never (or rarely)
changed, such as system initialization files.
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Figure 10.22 revised. The ROM family.
Data written by the
user, and can be
changed with some
difficulty.
Data written by
the manufacturer,
and can never be
changed.
Floyd, Digital Fundamentals, 10th ed
Data written by the
user, and can never
be changed.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Read-Only Memory (ROM)
A ROM symbol is shown with typical inputs and outputs.
The triangles on the outputs indicate it is a tri-stated device.
Address
input lines
A0
ROM 256´4
Data
output
lines
0
A1
Valid address on input lines
A4
A5
ta
Data
outputs
Valid data on output lines
Data output
transition
Chip
select
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0
A 255
A6
A7
E0
E1
O0
O1
O2
D
A3
D
Address
input lines
Address transition
D
A2
D
To read a value from the ROM, an address
is placed on the address bus, the chip is
enabled, and a short time later (called the
access time), data appears on the data bus.
O3
7
&
EN
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PROMs, UV EPROMs and EEPROMs
PROMs are programmable ROM, in which a fused link is
burned open during the programming process. Once the
PROM is programmed, it cannot be reversed.
0
D
D
0
A 2047
D
D
D
D
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A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D
Another type of erasable PROM is the EEPROM,
which can be erased and programmed with
electrical pulses.
EPROM
2048 ´ 8
VPP
D
A UV EPROM can be erased by exposure to
UV light through a window. To program it, a
high voltage is applied to VPP and OE is
brought LOW.
O0
O1
O2
O3
O4
O5
O6
O7
10
CE/PGM
&
OE
EN
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Figure 10.29 MOS PROM array with fusible links. (All drains are commonly connected to VDD.)
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Flash Memory
Flash memories are high density read/write memories that
are nonvolatile. They have the ability to retain charge for
years with no applied power.
Floating
gate
Flash memory uses a MOS transistor
with a floating gate as the basic storage
cell. The floating gate can store charge
(logic 0) when a positive voltage is
applied to the control gate. With little or
no charge, the cell stores a logic 1.
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Drain
Control
gate
– –
– –
– –
– –
– –
– –
MOS
transistor
symbol
Source
logic 0 is stored
–
–
logic 1 is stored
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
FIFO Memory
FIFO means first in-first out. This type of memory is
basically an arrangement of shift registers. It is used in
applications where two systems communicate at different
Memory array stores
rates.
64 4-bit data words
64-bit shift register
I0
Data I 1
input I 2
I3
Input
buffers
64-bit shift register
64-bit shift register
Output
buffer
O0
O1
O2
O3
Data
output
64-bit shift register
Control lines
Shift in (SI)
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Input
control
logic
Control lines
Marker register
and controls
Output
control
logic
Output ready (OR)
Shift out (SO)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
LIFO Memory
LIFO means last in-first out. In microprocessors, a portion
of RAM is devoted to this type of memory, which is called
the stack. Stacks are very useful for temporary storage of
internal registers, so that the processor can be interrupted
but can easily return to a given task.
A special register, called the
stack pointer, keeps track of the
location that data was last stored
on the stack. This will be the
next data to be taken from the
stack when needed.
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Stack pointer
FFEC
0 0 1 1 0 1 0 0 Top-of-stack
0 0 0 1 0 0 1 0
0 0 0 0 0 0 0 0
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Memory versus Storage
•“Memory” refers to semiconductor devices of the
kinds we’ve been discussing (RAM, ROM, Flash).
•“Storage” refers to non-semiconductor non-volatile
devices used to store huge quantities of data.
Major categories include:
•Magnetic disk (such as computer hard drives)
•Magnetic tape
•Optical disk (CDs and DVDs)
Magnetic Hard Drive
The magnetic hard drive is the backbone of computer mass
storage and is applied to other devices such as digital video
recorders. Capacities of hard drives have increased
exponentially, with 1 TB (1 trillion bytes!) drives available
today.
Spindle
Platters
Actuator
arms
Read/Write
heads
Case
Hard drive with cover removed
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Optical Storage
The compact disk (CD) uses a laser to burn tiny pits into
the media. Surrounding the pits are flat areas called lands.
The CD can be read using a low-power IR laser that detects
the difference between pits and lands.
Binary data is encoded with a special method
called negative non-return to zero encoding.
A change from a pit to a land or a land to a pit
represents a binary one, whereas no change
represents a zero. A standard 120 mm CD can
hold approximately 700 MB of data.
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