Transcript A CCD-based vertex detector Chris Damerell on behalf of the LCFI Collaboration • Project overview and design principles • R&D programme • Development of.

A CCD-based vertex detector
Chris Damerell on behalf of the LCFI Collaboration
• Project overview and design principles
• R&D programme
• Development of novel CCDs and readout electronics
• Development of thinnest possible detector layers
• Physics studies
• Summary and future plans
July 14 2003
US LC Workshop Cornell U – Chris Damerell
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Project overview
• Linear Collider Flavour ID Collaboration: Bristol U, Lancaster U,
Liverpool U, Oxford U, QMUL and RAL
• R&D assumes up to 5 CCD development cycles at intervals of
~20 months
• Initially funded by PPARC for £2.3M for 3 yrs from April 2002
(£700K equipment, £1600K PPARC manpower)
• Synergy with recent PPARC plans to play a major part in the LC
BDS (beam delivery system)
• Working to develop closer ties between other regional VTX
activities. Our international phone conference at time of US
workshop at UT Arlington was a major success
• Looking forward to one international collaboration to build the
LC vertex detector, once prototype ladders have enabled the
technology choice to be made
• One major unknown in the decision process is the accelerator
technology
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US LC Workshop Cornell U – Chris Damerell
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Design principles
• 5 layers, inner layer at radius 12-15 mm
• 3-hit coverage to cosq = 0.96
• thin layers (<0.1% X0 ) for minimal mult scatt and g conversions
July 14 2003
US LC Workshop Cornell U – Chris Damerell
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• silicon pixels of size ~ 20 mm square for low cluster-merging in jets
• support structure with micron precision/stability (specially important
for oblique tracks near ladder ends)
• on-detector signal processing, so almost no external connections
• power dissipation measured in few tens of watts, so gas cooling
sufficient (
vital for low material budget)
• ‘adequate’ radiation hardness
• readout time ~ 5 ms for JLC/NLC (between bunch trains)
~ 50 ms for TESLA (20 frames/bunch train)
•
  4
4
p sin3 / 2 q
• crucial for efficient charm ID (1-prong decays), vertex charge (Bs),
but quantitative physics examples still being worked on …
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US LC Workshop Cornell U – Chris Damerell
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Novel CCDs and readout electronics
• CCD sizes similar to SLD, but readout needs to be 20-2000 times faster
• eliminate bulky electronics which would degrade fwd tracking and
calorimetry
• total of 800 Mpixels, cf 307 Mpixels for SLD
• TESLA readout requirement stimulated concept of ‘column parallel’
operation
•
innovative CCD/CMOS hybrid. If successful, this architecture
may also be preferred for NLC/JLC. However, for this case, the
conventional architecture with a multiple-output linear register should
also be evaluated
July 14 2003
US LC Workshop Cornell U – Chris Damerell
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M
N
N
“Classic CCD”
Readout time  NM/Fout
Column Parallel CCD
Readout time = N/Fout
• Max possible readout speed, for given noise performance
• Readout IC (amp+ADC on 20 mm pitch) only became available
with deep submicron CMOS technology
• TESLA requires parallel register clocking at 50 MHz: 1 MHz is
fine for NLC
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US LC Workshop Cornell U – Chris Damerell
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 electronics only at the ends of the ladders
 bump-bonded assembly between thinned CPCCD and readout chip
 readout chip does all the signal processing, yielding sparsified digital data
 CPCCD is driven with high frequency, low voltage clocks
 low inductance layout required for clock delivery
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US LC Workshop Cornell U – Chris Damerell
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Standard 2-phase Field-enhanced 2-phase implant
implant
(high speed)
Features of our first CPCCD:
Metallised gates
(high speed)
• 2 different charge transfer regions
• 3 types of output circuitry
Source
followers
Direct
2-stage
source
followers
Readout
ASIC
Source
followers
Metallised gates
(high speed)
Direct
Readout
ASIC
To pre-amps
• Independent CPCCD and readout
chip testing possible:
•without readout chip - use
external wire bonded electronics
• without bump bonding - use
wire bonds to readout chip
• finally, bump-bonded
• Different readout concepts can be
tested (direct charge sensing, and
voltage sensing via source follower)
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US LC Workshop Cornell U – Chris Damerell
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CPC-1 delivered & under test
Direct connections and 2-stage source followers
1-stage source followers and direct connections on
20 μm pitch
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US LC Workshop Cornell U – Chris Damerell
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US LC Workshop Cornell U – Chris Damerell
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Single pixel events seen in one column of CPC-1
with 2 V peak-peak clocks
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US LC Workshop Cornell U – Chris Damerell
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Wire/bump bond pads
Charge Amplifiers
Voltage Amplifiers
250 5-bit flash ADCs
FIFO
Wire/bump bond pads
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US LC Workshop Cornell U – Chris Damerell
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US LC Workshop Cornell U – Chris Damerell
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Thinnest possible detector layers
3 approaches
•
Unsupported silicon
•
Semi-supported silicon
•
Supported silicon
Unsupported approach attractive – ‘like wires in a drift chamber’
Works beautifully along ladder length (sagitta stability around 2 microns)
However, processed thin CCD is not like a wire: it’s an inhomogeneous
membrane in which transverse stresses may lead to somewhat
uncontrollable shape
Also, we have concerns about handling issues, for attaching readout chips
etc
Not abandoned, but semi-supported approach may be more practicable
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Beryllium substrate with adhesive balls
Thinned CCD (  20 μm)
CCD brought down
Shims
Assembly after shim removal and curing
Adhesive
0.2mm
Beryllium substrate (250 μm)
1 mm
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US LC Workshop Cornell U – Chris Damerell
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Physics studies
The design of the VXD should be driven by the physics requirements:
• 4 configurations, 5 layer single thickness and 4 layer double thickness,
and other combinations
• make single muon and pion tracks in Brahms for all momenta and
angles. Fit the distributions
• include the parametrizations in Simdet
• biggest effect comes from removal of the inner layer
• provide to physics groups
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US LC Workshop Cornell U – Chris Damerell
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5layers
•
•
4 layers,
double
Clear performance difference between configurations
Charm suffers most, B tagging is “easy”
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US LC Workshop Cornell U – Chris Damerell
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•
New procedure to attach track to
vertices
•
Charged B, up to 89% correct tag,
6-8% worse for 4 layer double
thickness configuration
•
Charged D, excellent purity, less
difference between configurations
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US LC Workshop Cornell U – Chris Damerell
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•
Neutral B: dipole
•
Maintain, develop and improve
tools
•
Provide them to the physics
community so we can get feedback on detector parameters from
various physics channels
•
Make a transition to Java/JAS
environment
July 14 2003
US LC Workshop Cornell U – Chris Damerell
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Summary and future plans
• Fast CCDs:
•
much to study with CPC-1
• tentative plan for design/production of CPC-2 (including detectorscale prototypes, 10x2 cm2) Oct 2003-June 2004
•
readout chips CPR-1 and CPR-2 all we need in medium term future
• Thin ladders:
• semi-supported assemblies with a well-behaved adhesive may be
fine, including satisfying the bump-bonding assembly requirements
• numerous alternative ideas, some (fortunately) being pursued by
other groups – notably the DEPFET collaboration
• Physics studies:
•
totally dependent on available effort, a small but dedicated team
• Major opportunities for wider collaboration in all areas, and
informally it is happening
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