Oregon State UNIVERSITY OSU Design Techniques for Radiation Hardened Phase Locked Loops Anantha Nag Nemmani, Martin Vandepas, Kerem Ok, Kartikeya Mayaram and Un-Ku Moon 2005 MAPLD International.

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Transcript Oregon State UNIVERSITY OSU Design Techniques for Radiation Hardened Phase Locked Loops Anantha Nag Nemmani, Martin Vandepas, Kerem Ok, Kartikeya Mayaram and Un-Ku Moon 2005 MAPLD International.

Oregon State
UNIVERSITY
OSU
Design Techniques for Radiation Hardened
Phase Locked Loops
Anantha Nag Nemmani, Martin Vandepas,
Kerem Ok, Kartikeya Mayaram and Un-Ku Moon
2005 MAPLD International Conference ◊ Ronald Reagan Building and International Trade Center
Washington, D.C. ◊ September 7-9, 2005
Electrical Engineering and Computer Science
Oregon State University
Effects
(c)
• Accumulation of charge in gate oxide
– Vth NMOS ↓ & Vth PMOS ↑
900
700
600
500
400
300
0
0.5
1
1.5
2
2.5
Control Voltage (V)
Tuning curves of Lee/Kim Ring oscillator
before and after radiation.
Digital PLL
Digital Loop
Filter
in
PFD
+
TDC
DCAO
20.3
20.3
4
2
0
19.8
19.9
20
20.1
20.2
20.3
20.3
4
2
0
19.8
19.9
20
20.1
20.2
20.3
20.3
4
2
0
19.8
19.9
20
20.1
20.2
Time ( s)
Control Voltage
20.3
FREF
FDIV
0
19.8
19.9
20
20.1
20.2
2
19.9
20
20.1
20.2
4
2
0
19.8
19.9
20
20.1 20.2
Time ( s)
Control Voltage
1
0.4
0.3
0.2
15
20
25
0.5
15
30
R
Vfine
V
SEE on control node
Digital Loop Filter
UP
dT
4dT
128dT
DN
Vcoarse
Vcoarse
Vfine
1X
2X
Vo-
Vd
 z
-1
Gn
1-z
-1
Vctrl
2 fLS BT R
0
Vi+
D
Q
Q
Q
Q

UP+DN
2 X
Pseudo-thermometer Encoder
DF
• Fine tuning current DAC
• 6 fine bits + 6 coarse bits
out
Openloop gain
out (z) 1
TR
α  β  αz1 z 1
 Gn
f LSBTR
2
in (z) N dT
1  z 1

β
 ω z TR
α
Control word
TDC Output



ω UGB 
K CP  G n
Proportional
VCTRL (z)
β 

 Gn  α 
1 
Vd (z)
 1 z 
Majority
D
/32
Q
R
U
V
D
PFD
TR
f LSB
dT
• Self calibration
– Calibrate Kdig to the desired value
1 TR
1
f LSB 1 
N dT
tan2 (Φ M )
20
2
Majority
/64
0dB
10
-180+PM
5
-135
-180
0
0
z
UGB
Frequency (  )
F
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
B
C
A
B
C
A
B
C
B
C
A
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Layout
D
PE<k>
dT
dT
A
4dT
B
128dT
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q
Co
Q<k>
S
Ci
D
Clk
Q
M aj
Decision
M aj
D
Q
D
Q
2
M aj
S GN
Majority
Q
D
Q
D
Pseudo-thermometer Encoder
PE
A
0.1
Time (sec)
Voting
A B C
Model
Simulink
15
H( )
LSB
dT FR
Operation of a TDC
Exponential delay chain
dT
2
Decision
Q
• Type – II loop filter
Single Event Hardening
SEE
D
00001111
Normalizing gain
SEE
Q
XXXX
1
-5
x 10
Response to frequency step at the input. Simulink
Agrees with mathematical model
Matching delay
D
Out
Integral gain
Q
SEE
16-bit
ω UGB
ωz 
tan(Φ M )
CPPLL Analogy
out (s) K CP s  ωz 

in (s)
Ns2
Redundancy & Majority Voting
D
Accumulator
D8
For optimum performance
Phase margin - ΦM
H( )
3. Loop filter:
• Loop parameters
– fLSB & dT – Process dependent
– Gn, α & β – Digital constants
• Loop dynamics are dependent only dependent
on:
T f
D7
Analysis Verification
2. Phase detector:
Vd 1 TR

d 2π dT
Radiation Hardening
D6
DCAO resolution
o (z)
z 1
 2π f LSBTR
VCTRL (z)
1  z 1
N
D
D5
Exponential delay chain
Latches
Sign detection
Pseudo-thermometor encoder
Incremental phase accumulated
-1
Q
D4
Phase Error
•
•
•
•
Integral gain
D3
N
2

D2
DF
DF
1
Normalizing gain
PE
D1
SGN
Q
Gn
UP+DN
N
4X
Vi-
N
Self-Calibration
D
PE
• Lee/Kim delay cell
• Fine/Coarse tuning
1-z
D
Vo+
DF
z-1
D
CTRL
y(t)
Vfine
2  dT
K dig  G n
dT
D
o [n  1]  o [n] 2π f LSBTR VCTRL [n]
vco
dT
11-bit
Proportional gain
SGN
1. DCAO:
R
25
Time ( s)
Exponential delay chain
U
PFD
Analysis
T
20
Time ( s)
Matching delay
• Digitally controlled analog oscillator (DCAO)
• Time-to-digital converter (TDC)
• Digital loop filter
out
20.2
4
• Transient error currents
• Modelled as sum of
exponential current sources
D
-
20.1
Adder
Frequency Divider
+
20
LF(z)
N
+
20.2
Time-to-digital converter
Rfine
d
20.1
SEE on last stage of frequency divider
PM1
in
20
2
0
19.8
Digitally controlled analog oscillator
out
19.9
4
+ - +
+ ++-+
+ - +
• Change in chargepump
current
• Loop parameters changed
as a result
• Loop transfer function
altered
800
0
19.8
UP
(b)
Frequency (MHz)
Bulk
– Change in nominal frequency
and VCO gain
19.9
2
DN
1000
20.3
4
2
0
19.8
4
Vctrl
1100
Oxide
D
FDIV
Pre-rad Body
Post-rad Body
Pre-rad Float
Post-rad Float
Sim
S
FREF
• VCO tuning curves shift
1200
Poly
(a)
G
VG
UP
VG
SEE on PLLs
DN
VG
Single Event Effects (SEE)
Effect on Phase Locked Loops (PLLs)
Vctrl
Total Ionization Dose (TID)
P hase E r r or
Time-to-digital converter
Frequency Divider
MAPLD 2005/228
Accumulator
30