Transcript On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal ASRC Aerospace.

On the Model-centric Design and Development
of an FPGA-based Spaceborne Downlink Board
Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal
ASRC Aerospace Corp.
6303 Ivy Lane, Suite 800
Greenbelt, MD 20770
{robert.jones, roman.machan, tahsin.lin, ed.leventhal}@akspace.com
Jones
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Key Points

About the SMART approach to model-centric
engineering design and development

Uses formal (mathematical and therefore unambiguous)
descriptions of a system throughout its development




Provides model checking and numerical analysis
Facilitates concept formulation, trade studies, and rapid
prototyping before committing to hardware and software
Successfully applied to an FPGA-based downlink
system designed for space applications
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Petri nets, queuing networks, data- and control-flow graphs,
finite automata, Markov chains, or user-defined formalisms
Example models constructed using Petri nets
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Petri Net
Model
token
p1

Bipartite graph of
places and transitions
connected by arcs

Marking of places
with tokens provides
state
transition
t1

place
p2
p3
t4

t2
t3
p4
p5
t5
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
Transitions are active
when sufficient tokens
are present or absent
from input places
Transitions then
fire, thus removing
tokens from input
places and
depositing them to
output places
Underlying State Machine
p1
fires
p2p3
t3
t2
t4
t2t3
p4p3
p2p5
t4
t3
Firing may be delayed
randomly or deterministically
3
t1
marking
p4p5
t2
t5
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The SMART Approach
Stochastic Model-Checking Analyzer
for Reliability and Timing (SMART)
Deployment – Preservation and maturation of
models aid documentation,
operation, and maintenance
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Integrate
Low-level
Integration – Aided by well-defined interfaces
and architecture
FPGA
Iteration – Repeat steps as necessary to refine
modeling and design details
VHDL
Testing – Cases, coverage, and acceptance
SystemC
Realization – Allocate functions to resources
Petri Net
Intermediate
Analysis – Performance tradeoffs
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Analytical
Simulation
Verification – Modeling the system right
Model Checking
Execution
Validation – Modeling the right system
Model Analysis and Testing
Validation
High-level
Capture – Well-defined system requirements
and design specification
Requirements
Downlink Dataflow and Queuing
32-bit Input Data from CompactPCI Bus
Interrupt on Input Queue status or queuing errors
Downlink Ready when Input Queue is at most 1/4 full
High-speed
Downlink Board
USES Bypass
15 bits
Input Function
66 MW/s
Input
Queue
1K32
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20 MB/s
USES
20 MS/s
(S=samples)
LSBs
USES
Queue
VCDU
Function
2K16
Output
Queue
10 MB/s
80 Mb/s
CADU
LVDS
DRVR
Function
Output
Data
Serial
Bit
Stream
4K8
LSBs
Queue
Reed-Solomon
Encoder
4K8
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Input Arrival and Buffering
Transfers
from Sensor
Module
Access Bus
word (w) = 16 bits
Burst
Arrival
Downlink Ready
¼Bi + 1
1K
Buffer
Next
Block
Block
Write (32 bits)
2
(words)
16 Mw/s burst
10 Mw/s average
Delay
1 cycle
5 cycles
Preempt
Active
Transfer
Done
Other
Use
Busy
Use
Bus
Idle
Inactive
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Downlink
Input
Queue
State of PCI Bus
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Resume
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Input Preprocessing
¾Bu
Process begins
with sufficient data
Input
Queue
Unpack
Input
Prevents USES Queue overflow
Remove
LSB
¼Bi+1
Sample
Data
20 Msamp/s
2
2 cycles
USES
VCDU
Word
Data
Function
8



USES
Queue
10 Mw/s
Each 2 KB of data is encoded
LSBs
1 cycle
LSBs
Write
into a compressed source
Queue
LSBs
packet for CCSDS transport
1 cycle
16-bit words are unpacked from PCI input
LSBs removed, queued, and later rejoined with packet data within
each Virtual Channel Data Unit (VCDU)
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USES Data Compression
IDbits
EndPac
Rice
Block
#(EndPac)
Evaluate
Block
N·(J - #(Ref))
J
Encoding
Info
Bit
Begin
Read
Code
BlkRef
(b)
Samples
#(Ref)
#(EndPac)
Block Count
Insert
(1-b)
16
Output
Reduce
Ref
Data
Ready
N
#(Code)
Reference Count
Write
RefPac
Delay
End
Packet
cond(0 < #(Code) < 16, 1, 0)
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USES
Queue
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VCDUs
VCDU
Header
Packet
Primary
Header
Packet
Secondary
Header
Packet Data Space
8 bytes
6 bytes
1 byte
1,085 bytes
¾Bo
Write
VCDU
Header
8
1 cycle
Data Queue
16x8
bits
Start
New
VCDU
Data Space
Write
Data
Start New
Packet
1092
1 cycle
8 cycles
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Output
Queue
State of
Writing
Packets
Aux
Queu
e
Create
(variable-length)
Data Packet
tk
tk
9
6
Writing
Packet Primary
Header
Header
Length
Complete
(variable-length)
Data Packet
Write
Header
2tk
Packet
Lengt
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Data Packets
Aux
Queue
First
Complete
(Compressed)
Data Packet
#
#
Write
Packet
Secondary
Header
1 cycle
1 cycle
¾Bd
Data
Queue
LSBs
Queue
Second
2 cycles
¾Bd
Write
LSBs
2
USES
Queue
128
Third
Write
USES
Packet
¾Bd
2
Start
New
Packet
Packet Length
tk(Packet Length)
Last
tk(Packet Length)
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Downlink Model Analysis
25
20
Maximum
Entropy Rate
14.7 bits/word
Mean
15
(4) Output to transmitter
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(2) USES Queue
Entropy Rate (bits per word)
of IR data, 0.6 wave no. around ZPD
(1) Input Queue
5.9 bits/word mean
5
(3) Output Queue
3.5 bits/word minimum
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