Transcript On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal ASRC Aerospace.

On the Model-centric Design and Development
of an FPGA-based Spaceborne Downlink Board
Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal
ASRC Aerospace Corp.
6303 Ivy Lane, Suite 800
Greenbelt, MD 20770
{robert.jones, roman.machan, tahsin.lin, ed.leventhal}@akspace.com
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Outline

SMART Approach to Model-centric Engineering

Formal Modeling with Petri Nets

Application to an FPGA-based Downlink Design

Summary
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Modern Formalisms
General Petri nets
conflicts, decisions,
concurrency, synchronization, …
Finite automata
(state machines)
Marked graphs
conflicts/decisions but
no concurrency
concurrency but no
conflicts/decisions
Data, control, process flow
graphs & queuing networks
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Petri Net

Bipartite graph, PN = (P, T, m0)

Set of places, P = {p1, p2, p3, p4, p5}

Set of transitions, T = {t1, t2, t3, t4, t5}

Arcs  PT  TP connecting

Places to transitions

Transitions to places

Tokens mark places and
defines the notion of state

Transitions fire when sufficient tokens
are present (or absent) from input
places, thereby removing tokens from
input places and depositing them to
output places
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t4
4
p1
t1
p2
p3
t2
t3
p4
p5
t5
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Reachability Graph
Underlying State Machine
p1

The notion of time is introduced
with firing delays

SPNs sojourn in markings for
some amount of time before
transitions fire, thus moving
the net to the next marking

Firing delays may be
deterministic or random
variables

Movement of the net among
markings with the passage of
time gives rise to a stochastic
process, which can be analyzed
t1
p2p3
t2
t4
t3
t2t3
p4p3
p2p5
t4
t3
t2
p4p5
t5
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Model Equivalents
Multi-server Queue
m
Petri Net
1
l
l
n
min(tk(p),m)·m
…
2
p
m
l
0
l
1
m
l
2
2m
l
…
3
3m
l
4m
mm
…
m+1
m
mm
l
l
l
mm
n
mm
Markov Chain
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The SMART Approach
Stochastic Model-Checking Analyzer
for Reliability and Timing (SMART)
Deployment – Preservation and maturation of
models aid documentation,
operation, and maintenance
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Integrate
Low-level
Integration – Aided by well-defined interfaces
and architecture
FPGA
Iteration – Repeat steps as necessary to refine
modeling and design details
VHDL
Testing – Cases, coverage, and acceptance
SystemC
Realization – Allocate functions to resources
Petri Net
Intermediate
Analysis – Performance tradeoffs
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Analytical
Simulation
Verification – Modeling the system right
Model Checking
Execution
Validation – Modeling the right system
Model Analysis and Testing
Validation
High-level
Capture – Well-defined system requirements
and design specification
Requirements
Benefits from Model Analysis
Qualitative

Quantitative
Exact state space analysis,

verifies logical correctness to
requirements specs




performance in the presence of
faults (other “bad” events)
Design function and form
Fault-tolerance and coverage
Insight to design alternatives



Process scheduling, driven by

data (control) flow and graphically
embedded



Availability, dependability
User-defined QoS
Reward (cost) of operating the
system over its mission time
Schedulability, computes graphtheoretic performance bounds of
“embedded” schedule
Exploits hidden concurrency
Determines correct, sufficient
synchronization and queuing
Alternative schedules imposed
via artificial dependencies
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Performability, measure of



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Critical path  end2end delay
Critical circuit  throughput
Resource utilization
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Downlink Dataflow and Queuing
32-bit Input Data from CompactPCI Bus
Interrupt on Input Queue status or queuing errors
Downlink Ready when Input Queue is at most 1/4 full
High-speed
Downlink Board
USES Bypass
15 bits
Input Function
66 MW/s
Input
Queue
1K32
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20 MB/s
USES
20 MS/s
(S=samples)
LSBs
USES
Queue
VCDU
Function
2K16
Output
Queue
10 MB/s
80 Mb/s
CADU
LVDS
DRVR
Function
Output
Data
Serial
Bit
Stream
4K8
LSBs
Queue
Reed-Solomon
Encoder
4K8
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VCDU Functional Dataflow
4Kx8 bits
Input
Function
VCDU Function
within FPGA
Idle data
16x8 bits
LSBs
Queue
Level < 1/4
Data
Queue
mux
(8) (8)
2Kx16 bits
USES
USES
Queue
Control
Output
Queue
Headers
4Kx8 bits
16x16 bits
EOP
EndBits
(5)
Fill8
(1)
(10)
DataRdy
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Counter
Auxiliary
Queue
Packet Word Length
10
20 MHz clock
20 MB/s
throughput
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Input Arrival and Buffering Model
Transfers
from Sensor
Module
Access Bus
word (w) = 16 bits
Burst
Arrival
Downlink Ready
¼Bi + 1
1K
Buffer
Next
Block
Block
Write (32 bits)
2
(words)
16 Mw/s burst
10 Mw/s average
Delay
1 cycle
5 cycles
Preempt
Active
Transfer
Done
Other
Use
Busy
Use
Bus
Idle
Inactive
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Downlink
Input
Queue
State of PCI Bus
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Resume
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Input Processing Model
¾Bu
Process begins
with sufficient data
Input
Queue
Unpack
Input
Prevents USES Queue overflow
Remove
LSB
¼Bi+1
Sample
Data
20 Msamp/s
2
2 cycles
USES
VCDU
Word
Data
Function
8
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USES
Queue
10 Mw/s
Each 2 KB of data is encoded
LSBs
1 cycle
LSBs
Write
into a compressed source
Queue
LSBs
packet for CCSDS transport
1 cycle
16-bit words are unpacked from PCI input
LSBs removed, queued, and later rejoined with packet data within
each Virtual Channel Data Unit (VCDU)
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Input Queuing Performance
High Entropy
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Nominal Entropy
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Summary of Downlink Model Analysis
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20
Maximum
Entropy Rate
14.7 bits/word
Mean
15
(4) Output to transmitter
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(2) USES Queue
Entropy Rate (bits per word)
of IR data, 0.6 wave no. around ZPD
(1) Input Queue
5.9 bits/word mean
5
(3) Output Queue
3.5 bits/word minimum
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USES Entropy Encoding Model
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Based on the Universal Source Encoder for Space (USES)
C(n) = (E(n) –1)J/16 code words per nth packet
E(n) = mean entropy rate (bits/word)
USES Queue
J = block size (samples/block)
C(n)
Encode
Block
Word Count
J cycles
C(n)
Sample
Data
Read
Sample
Evaluate
Block
tk
Aux Queue
tk
Block Count
tk
Packet Index
n
64
J
1 cycle
J
Next Sample
BlkRef·RefPac
= 64 blocks/word
2J
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Detailed Functional Model of USES
IDbits
EndPac
Rice
Block
#(EndPac)
Evaluate
Block
N·(J - #(Ref))
J
Encoding
Info
Bit
Begin
Read
Code
BlkRef
(b)
Samples
#(Ref)
#(EndPac)
Block Count
Insert
(1-b)
16
Output
Reduce
Ref
Data
Ready
N
#(Code)
Reference Count
Write
RefPac
Delay
End
Packet
cond(0 < #(Code) < 16, 1, 0)
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USES
Queue
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USES Queuing Performance
High Entropy
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Nominal Entropy
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VCDU Model
VCDU
Header
Packet
Primary
Header
Packet
Secondary
Header
Packet Data Space
8 bytes
6 bytes
1 byte
1,085 bytes
¾Bo
Write
VCDU
Header
8
1 cycle
Data Queue
16x8
bits
Start
New
VCDU
Data Space
Write
Data
Start New
Packet
1092
1 cycle
8 cycles
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Output
Queue
State of
Writing
Packets
Aux
Queu
e
Create
(variable-length)
Data Packet
tk
tk
18
6
Writing
Packet Primary
Header
Header
Length
Complete
(variable-length)
Data Packet
Write
Header
2tk
Packet
Lengt
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Data Packet Creation Model
Aux
Queue
First
Complete
(Compressed)
Data Packet
#
#
Write
Packet
Secondary
Header
1 cycle
1 cycle
¾Bd
Data
Queue
LSBs
Queue
Second
2 cycles
¾Bd
Write
LSBs
2
USES
Queue
128
Third
Write
USES
Packet
¾Bd
2
Start
New
Packet
Packet Length
tk(Packet Length)
Last
tk(Packet Length)
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Synchronous CADU Model
Demands steady
supply of VCDUs
Read
VCDU
Output
Queue

Channel Access Data Units
(CADUs) are RS protected,
sync prefixed, and
1264 bytes long
Output Queue
is demand driven
by synchronous
CADUs to maintain
80 Mb/s output
bit-data stream
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164 cycles
Write
RS Code
and ASM
1100
1 cycle

VCDU
Length
(bytes)
VCDU
Function
1100
Reed-Solomon
Encoder
10 MHz
Adds 160 byte RS code
1 cycle per byte delay,
1100 + 160 cycles total
Standard FIFO
(4Kx8 bits)
Output
Queue
20 MHz
20 MBps throughput
20
CADU
Data
Function
Clock
80 Mbps
80 MHz nom
10 MHz
10 MBps input rate
80 Mbps output rate
Adds 4 byte Attached Sync Marker
1264 clock cycles of work
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Output Queuing Performance
High Entropy
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Nominal Entropy
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Summary

Petri net modeling with the SMART tool provides a
formal (mathematical and therefore unambiguous)
description of a system throughout its development

The engineering process therefore benefits from

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
Ensuring precise requirements specification

Model checking to ensure logical correctness

Quantified QoS measures that facilitate trade studies

Rapid, model-based prototyping before committing to
hardware or software
Successfully applied to an FPGA-based downlink
system designed for space applications
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