Transcript DAQ for KEK beam test M.Yoshida (Osaka Univ.) Components • VLPC readout – Stand Alone Sequencer (SASeq) • Slow – Buffering VLPC data with.

DAQ for KEK beam test
M.Yoshida (Osaka Univ.)
Components
• VLPC readout
– Stand Alone Sequencer (SASeq)
• Slow < 100Hz
– Buffering VLPC data with VME interface
• Fast > 10kHz expected
• TOF counter readout
ethernet
– CAMAC ADC/TDC in KEK elec. Pool
– Readout via VME with VME-CCP interface module
• CCP : max 10 MByte/sec
• DAQ software
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UniDAQ developed by KEK
Running on Linux
Server (Evbuilder) + Clients (Collectors)
Already installed in PC at D0 test stand
Need to write collectors
EvBuilder
VME
VLPC
Collector
CAMAC
TOF
Collector
TKO?
The other
Detectors
Linux PC
System Overview
AFE II (L)
PCI-VME
1553
SASeq #1
U
VME BUS
6
SASeq #2
CAMAC-VME
AFE II Control
VLPC backplane
Slow Control
VLPC Cassette #1
AFE II (R)
8x64 ch
AFE II (L)
8x64 ch
LVDS-VME #２
1024 ch
8x64 ch
VLPC Cryostat
Serialized ADC DATA
LVDS-VME #３
LVDS-VME #４
4x8bit = 32 bit / board
1024 ch
VLPC Cassette #2
AFE II (R)
LVDS-VME #1
8x64 ch
CAMAC crate
LVDS  VME
• MCM puts serialized ADC data
– Need to deserialize before FIFO
• Solution 1:
– Custom-made VME board
• [MCM  serialize]  cable  [deserialize  FIFO]  VMEbus
– Under development in Fermilab
• Solution 2:
– Use KEK-FIFO board
• 32-bit inputs / board
• [MCM  serialize]  cable  [deserialize]  cable  [FIFO board]
 VMEbus
– Under development decoder board to deserialize ADC data
D0 FIFO board
FIFO/SRAM
VME interface
FPGA
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128-p metric conn.
AMP 1-352272-1
3:21 LVDS receiver (66MHz)
SN65LVDS96
Newly-designed by fermilab
Need to design
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VME interface
FPGA program
VME bus
KEK FIFO board
(GNV-100)
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Already exist / debugged
Standard VME 6U module
NIM ext. clock input
NIM trigger input
TTL 2x 16 bit data input
Operation in 100MHz
Depth: 65K x 32 bits
– FIFO: IDT72V36100
• Need LVDS decoder
LVDS-TTL module
(deserialize)
• Need +5/-5V power supply
– Standard VME 6U board
• 2x 8-pin deferential LVDS inputs
• 2x 16 bit TTL outputs
• NIM clock out
NIM CLOCK OUT
CLKOUT
A0-A2
D0-D7
CLKIN
CLKOUT
D10-D17
CN-34P
NIM CLOCK OUT
A0-A2
D0-D7
CLKIN
D10-D17
RJ-48
CN-34P
3:21 LVDS receiver (66MHz)
SN65LVDS96
DS90CR216A
NIM CLOCK OUT
Summary
• Started to design DAQ system for KEK
beam test in the summer of 2005
• Buffer module for VLPC data is under
development to increase DAQ rate up to
10 kHz
– D0 FIFO module
– KEK FIFO module + decoder board
• DAQ test / preparation in Nov. and Dec.
– The completed system will be sent to KEK