ESE370: Circuit-Level

Modeling, Design, and Optimization

for Digital Systems

Day 13: September 27, 2013 Variation 1 Penn ESE370 Fall2013 -- DeHon

Previously

• Understand how to model transistor behavior • Given that we know its parameters – V dd , V th , t OX , C OX , W, L, N A … C GCB C GC C GCS 2 Penn ESE370 Fall2013 -- DeHon

But…

• We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment (

e.g.

Temperature) 4.Parameters change with time (aging) Why I am more concerned with robustness than precision.

3 Penn ESE370 Fall2013 -- DeHon

Today

• Sources of Variation – Fabrication – Operation – Aging • Coping with Variation – Margin – Corners – Binning Penn ESE370 Fall2013 -- DeHon 4

Penn ESE370 Fall2013 -- DeHon

Fabrication

5

Variation Types

• Many reasons why things are different – Show up in many different ways.

• Scales – Wafer-to-wafer, die-to-die, transistor-to transistor • Correlations – Systematic, spatial, random (uncorrelated) 6 Penn ESE370 Fall2013 -- DeHon

Penn ESE370 Fall2013 -- DeHon Source: Noel Menezes, Intel ISPD2007 7

Process Shift

• Oxide thickness • Doping level • Layer alignment • Growth and Etch rates and times – Depend on chemical concentrations • How precisely can we control those?

• Vary machine-to-machine, day-to-day • Impact all transistors on wafer Penn ESE370 Fall2013 -- DeHon 8

Systematic Spatial

• Parameters change consistently across wafer or chip based on location • Chemical-Mechanical Polishing (CMP) – Dishing • Lens distortion 9 Penn ESE370 Fall2013 -- DeHon

FPGA Systematic Variation

• 65nm • Virtex 5 Penn ESE370 Fall2013 -- DeHon [Tuan et al. / ISQED 2010] 10

Oxide Thickness

[Asenov et al. TRED 2002] Penn ESE370 Fall2013 -- DeHon 11

Line Edge Roughness

• 1.2

m m and 2.4

m m lines From: http://www.microtechweb.com/2d/lw_pict.htm

Penn ESE370 Fall2013 -- DeHon 12

Optical Sources

• What is the shortest wavelength of visible light?

• How compare to 45nm feature size?

Penn ESE370 Fall2013 -- DeHon 13

Phase Shift Masking

Today’s chips use λ =193nm Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx

14 Penn ESE370 Fall2013 -- DeHon

Line Edges (PSM)

Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists 15 Penn ESE370 Fall2013 -- DeHon

Intel 65nm SRAM (PSM)

Source: Penn ESE370 Fall2013 -- DeHon

Statistical Dopant Placement Penn ESE370 Fall2013 -- DeHon 17 [Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans

• Random dopant fluctuation • Local oxide variation • Line edge roughness • Etch and growth rates – Stochastic process • Transistors differ from each other in random ways Penn ESE370 Fall2013 -- DeHon 18

Penn ESE370 Fall2013 -- DeHon Source: Noel Menezes, Intel ISPD2007 19

Impact

• Changes parameters – W, L, t OX , V th • Change transistor behavior – W?

– L?

– t OX ?

I DS I DS

  

sat C OX W V GS

m

n C OX



W L

   

V GS



V T



V T

 

V DS V DSAT

2 

V

20 2 2

DS

   



Example: V

th • Many physical effects impact V th – Doping, dimensions, roughness • Behavior highly dependent on V th

I DS

 

sat C OX W V GS



V T



V DSAT

2 

I DS



I S

 

W L

 

e



V GS nkT



V T

/

q

   1 

e

  

V kT DS

/

q

     1  

V DS

 21

V

th

Variability @ 65nm

Penn ESE370 Fall2013 -- DeHon 22 [Bernstein et al, IBM JRD 2006]

Impact of V

th

Variation?

• Higher V TH ?

– Not drive as strongly – I d,vsat  (V gs -V TH ) – Performance?

Penn ESE370 Fall2013 -- DeHon 23

Impact Performance

• V th  I ds  Delay (R on * C load ) Penn ESE370 Fall2013 -- DeHon 24

Impact of V

th

Variation

Penn ESE370 Fall2013 -- DeHon Think NMOS Vgs = Vdd 25

FPGA Logic Variation

• Xilinx Virtex 5 • 65nm • Altera Cyclone-II • 90nm [Tuan et al. / ISQED 2010] Penn ESE370 Fall2013 -- DeHon [ Wong, FPT2007 ] 26

Variation in 65nm FPGAs

[Gojman, FPGA2013] DeHon May 2013 27

LUT-to-LUT Same LAB

• LAB (27,22) average 5% variation [Gojman, FPGA2013] DeHon May 2013 28

• LAB (27,22)

Delay Map

[Gojman, FPGA2013] DeHon May 2013 29

Two LUT2LUT across Chip

30 DeHon May 2013

Reduce Vdd (Cyclone IV 60nm LP)

[Gojman, FPGA2013] DeHon May 2013 31

Impact of V

th

Variation?

• Lower V TH ?

– Not turn off as well  leaks more

I DS



I S

 

W L

Penn ESE370 Fall2013 -- DeHon  

e



V GS nkT



V T

/

q

   1 

e

  

V kT DS

/

q

     1  

V DS

 32 

2004

Penn ESE370 Fall2013 -- DeHon Borkar (Intel) Micro 37 (2004) 33

Penn ESE370 Fall2013 -- DeHon

Operation

Temperature Voltage 34

Temperature Changes

• Different ambient environments – January in Maine – July in Philly – Air conditioned machine room • Self heat from activity of chip • Quality of heat sink (attachment thereof)

I DS



I S

 

W L

 

e



V GS nkT



V T

/

q

   1 

e

  

V kT DS

/

q

     1  

V DS

 Penn ESE370 Fall2013 -- DeHon 35 

Self Heating

Penn ESE370 Fall2013 -- DeHon Borkar (Intel) Micro 37 (2004) 36

Thermal Profile for Processor

Penn ESE370 Fall2013 -- DeHon 37 [Reda/IEEE Tr Emerging CAS v1n2 2011]

How does temperature impact on-current?

• High temperature – More free thermal energy • Easier to conduct • Lowers V th – Increase rate of collision • Lower saturation velocity • Lower saturation voltage • Lower peak I ds  slows down • One reason don’t want chips to run hot Penn ESE370 Fall2013 -- DeHon 38

Temperature and I

ds Penn ESE370 Fall2013 -- DeHon 39

How does temperature impact leakage current?

• High temperature Lowers V th

I DS



I S

 

W L

 

e



V GS nkT



V T

/

q

   1 

e

  

V kT DS

/

q

     1  

V DS

 Penn ESE370 Fall2013 -- DeHon 40 

Voltage

• Power supply isn’t perfect • Differs from design to design – Board to board?

– How precise is regulator?

• IR-drop in distribution • Bounce with current spikes Penn ESE370 Fall2013 -- DeHon 41

Penn ESE370 Fall2013 -- DeHon

Aging

Hot Carrier NBTI 42

Hot Carriers

• Trap electrons in oxide – Also shifts V th Penn ESE370 Fall2013 -- DeHon 43

NBTI

• Negative Bias Temperature Instability – Interface traps, Holes • Long-term negative gate-source voltage – Affects PFET most • Increase V th • Partially recoverable?

• Temperature dependent Another reason not to run hot.

Penn ESE370 Fall2013 -- DeHon [Stott, FPGA2010] 44

Measured Accelerated Aging (Cyclone III, 65nm FPGA)

Penn ESE370 Fall2013 -- DeHon [Stott, FPGA2010] 45

Coping with Variation

Penn ESE370 Fall2013 -- DeHon 46

Variation

• See a range of parameters – L: L min – L max – V th : V th,min – V th,max Penn ESE370 Fall2013 -- DeHon 47

Impact of V

th

Variation

• Higher V TH – Not drive as strongly – I d,vsat  (V gs -V TH )

I DS

 

sat

• Lower V TH – Not turn off as well 

C OX W V GS

leaks more 

V T



V DSAT

2 

I DS

 

I S

 

W L

Penn ESE370 Fall2013 -- DeHon  

e



V GS nkT



V T

/

q

   1 

e

  

V kT DS

/

q

     1  

V DS

 48 

Variation

• Margin for expected variation • Must assume V th – Speed  can be any value in range assume V th slowest value I on,min =I on (V th,max ) I d,vsat  (V gs -V th ) V TH Penn ESE370 Fall2013 -- DeHon 49

Gaussian Distribution

From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg

50 Penn ESE370 Fall2013 -- DeHon

Impact

• Given – V th,nom = 250mV – Sigma 25mV • Probability of 100 transistor circuit in range when each has 96% prob. ?

• …when each has 99.8% probability?

Penn ESE370 Fall2013 -- DeHon 51

Impact

• Given – V th,nom = 250mV – Sigma 25mV • What maximum V th see for a circuit of should expect to – 100 transistors?

– 1000 transistors?

– 10 9 transistors?

Penn ESE370 Fall2013 -- DeHon 52

Variation

• See a range of parameters – L: L min – L max – V th : V th,min – V th,max • Validate design at extremes – Work for both V th,min and V th,max ?

– Design for worst-case scenario Penn ESE370 Fall2013 -- DeHon 53

Margining

• Also margin for – Temperature – Voltage – Aging: end-of-life Penn ESE370 Fall2013 -- DeHon 54

Process Corners

• Many effects independent • Many parameters • With N parameters, – Look only at extreme ends (low, high) – How many cases?

• Try to identify the {worst,best} set of parameters – Slow corner of design space, fast corner • Use corners to bracket behavior Penn ESE370 Fall2013 -- DeHon 55

Simple Corner Example

350mV What happens at various corners?

Vthp 150mV 150mV Vthn 350mV Penn ESE370 Fall2013 -- DeHon 56

Process Corners

• Many effects independent • Many parameters • Try to identify the {worst,best} set of parameters – E.g. Lump together things that make slow • Vthn, Vthp, temperature, Voltage • Try to reduce number of unique corners – Slow corner of design space • Use corners to bracket behavior 57 Penn ESE370 Fall2013 -- DeHon

Range of Behavior

• Still get range of performances • Any way to exploit the fact some are faster?

Delay Penn ESE370 Fall2013 -- DeHon 58

Speed Binning

Sell Premium Sell nominal Sell cheap Discard Delay Penn ESE370 Fall2013 -- DeHon 59

Idea

• Parameters Approximate • Differ – Chip-to-chip, transistor-to-transistor, over time • Robust design accommodates – Tolerance and Margins – Doesn’t depend on precise behavior 60 Penn ESE370 Fall2013 -- DeHon

Midterm 1

• Contents should not be a surprise – Identify CMOS/non-CMOS – Identify CMOS function – Any logic function  CMOS gate – Noise Margins – Circuit quasistatic configuration and switching delay Penn ESE370 Fall2013 -- DeHon 61

Admin

• Midterm Monday – 7—9pm in Towne 309 • Previous midterm – Solutions linked to 2010--2012 syllabus • But only one midterm in 2010 so parts more advanced than where we are now • Review on Sunday – 5:30pm Penn ESE370 Fall2013 -- DeHon 62