Transcript L16 – Testbenches for state machines VHDL Language Elements  More examples    HDL coding of class examples Testbench for example Testing of examples – testbench construction  Note.

L16 – Testbenches for
state machines
VHDL Language Elements
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More examples
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HDL coding of class examples
Testbench for example
Testing of examples – testbench construction
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Note trade off and difference in Mealy vs Moore
implementation from simulation results
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Constructing simple testbenches – general rules
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Ref: text Unit 10, 17, 20
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More examples
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Consider the state machine we designed earlier for
detecting an input that ends in the sequence 101.
Developed both Mealy and Moore implementations.
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Now translate these to VHDL
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The ENTITY – the same ports
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ENTITY mealy101 IS
PORT (clk,x : IN bit; z : OUT bit);
END mealy101;
ENTITY moore101 IS
PORT (clk,x : IN bit; z : OUT bit);
END moore101;
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Start the architecture
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The declarative region
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ARCHITECTURE one OF mealy101 IS
TYPE state_type IS (s0,s1,s2);
SIGNAL state,next_state : state_type;
BEGIN
ARCHITECTURE one OF moore101 IS
TYPE state_type IS (s0,s1,s2,s3);
SIGNAL state,next_state : state_type;
BEGIN
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The F/F process
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The state elements
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--state elements mealy
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;
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--state elements moore
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;
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The next state processes – Mealy
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--next state logic mealy
PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
WHEN s1 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
WHEN s2 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
END CASE;
END PROCESS;
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The next state process – Moore
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PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s1;
END IF;
WHEN s1 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
WHEN s2 => IF (x='0') THEN next_state <= s0;
ELSE next_state <= s3;
END IF;
WHEN s3 => IF (x='0') THEN next_state <= s2;
ELSE next_state <= s1;
END IF;
END CASE;
END PROCESS;
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The output logic - Mealy
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-- output logic - mealy machine
PROCESS (state,x)
BEGIN
CASE state IS
WHEN s0 => z<='0';
WHEN s1 => z<='0';
WHEN s2 => IF (x='1') THEN z<='1';
ELSE z<= '0';
END IF;
END CASE;
END PROCESS;
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The output logic - Moore
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--output logic - Moore machine
PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => z <= '0';
WHEN s1 => z <= '0';
WHEN s2 => z <= '0';
WHEN s3 => z <= '1';
END CASE;
END PROCESS;
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Creating a testbench
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Start with the ENTITY
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As the testbench is the top unit there is no interface.
Process within testbench generate stimulus and possibly
check response and generate reports.
ENTITY tb101 IS
END tb101;
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Declarations
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The declrative region – declare DUTs
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ARCHITECTURE one OF tb101 IS
--declare units to be tested
COMPONENT mealy101
PORT (clk,x : IN bit; z : OUT bit);
END COMPONENT;
FOR all : mealy101 USE ENTITY work.mealy101(one);
COMPONENT moore101
PORT (clk,x : IN bit; z : OUT bit);
END COMPONENT;
FOR all : moore101 USE ENTITY work.moore101(one);
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Declarative Region
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Declare signal to connect to DUT
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BOTH stimulus and response
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-- delcare input signals and input stream
SIGNAL xs : BIT_VECTOR (1 to 30) :=
('0','0','0','1','0','1','0','0','0','1','0','1','0','1','0','1',
'0','0','0','1','0','1','1','0','1','1','1','0','1','0');
SIGNAL x,z1,z2 : BIT;
SIGNAL clk : BIT :='1';
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Wire in DUT
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Instantiate components
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BEGIN
--Instantiate units
ml : mealy101 PORT MAP (clk,x,z1);
mo : moore101 PORT MAP (clk,x,z2);
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Set up clocks
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Set up a 50% duty cycle clock
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--Set up clock
clk <= NOT clk AFTER 5 ns;
50% duty cycle clock is easy as above
More complex clocks can be set up
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More complex clocks
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Use a process
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PROCESS -- clk starts set high
BEGIN
clk <= ‘1’;
WAIT FOR 5 ns; -- time high
clk <= ‘0’;
WAIT FOR 15 ns; --time low
END PROCESS;
This is a 25% duty cycle clock the is high 25% of the
period. Easy to adapt for any duty cycle and clock
period.
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The stimulus process
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--Stimulus process
PROCESS
BEGIN
WAIT FOR 1 ns;
FOR i IN 1 to 30 LOOP
x <= xs(i);
WAIT FOR 10 ns;
END LOOP;
WAIT FOR 10 ns;
WAIT;
END PROCESS;
Process grabs inputs from the input vector set up in the declarative region.
A good option when a simple sequence on a single signal.
More advanced techniques may be needed for complex machines.
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The simulation result
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The waveform – note clock edge versus X valid
time. ('0','0','0','1','0','1','0','0','0','1','0','1','0','1','0','1‘,'0','0','0','1','0','1','1','0','1','1','1','0','1','0');
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Simulation result 2
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If timing of clock edge versus input X is
shifted output can be different
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Demo of simulation
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A look at a live demonstration of Model Sim
for simulation of this machine.
Note that in Moore implementation output
seems to be delayed ~1 clock.
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Lecture summary
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HDL from code to simulation
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For the 101 sequence detector
Testbench for the sequence detector
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