Transcript L16 – VHDL for State Machines with binary encoding VHDL – binary encoded states  Another example      Counter – enumeration states Binary encoded states Gray Code Controlled counters Ref:

L16 – VHDL for State
Machines with binary
encoding
VHDL – binary encoded states
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Another example
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Counter – enumeration states
Binary encoded states
Gray Code
Controlled counters
Ref: text Unit 10, 17, 20
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Counter example
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Specification – Write a synthesizable VHDL
description of a 3-bit counter that counts from
0 to 7 in binary, i.e., 000, 001, 010, …, 110,
111.
A 3-bit counter has 8 states, so,s1, …, s8.
The state occur sequentially without control.
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Start the HDL
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This is a problem that one should be able to
do without a state diagram to start.
The entity
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ENTITY cnt3bit IS
PORT(clk : IN bit;
cnt : OUT bit_vector(2 downto 0));
END cnt3bit;
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The ARCHITECTURE
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ARCHITECTURE one OF cnt3bit IS
TYPE state_type IS (s0,s1,s2,s3,s4,s5,s6,s7);
SIGNAL state,next_state : state_type;
BEGIN
--F/F process
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;
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The next state process
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--next_state process
PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => next_state <= s1;
WHEN s1 => next_state <= s2;
WHEN s2 => next_state <= s3;
WHEN s3 => next_state <= s4;
WHEN s4 => next_state <= s5;
WHEN s5 => next_state <= s6;
WHEN s6 => next_state <= s7;
WHEN s7 => next_state <= s0;
END CASE;
END PROCESS;
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The output process
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--output process
PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => cnt <= "000";
WHEN s1 => cnt <= "001";
WHEN s2 => cnt <= "010";
WHEN s3 => cnt <= "011";
WHEN s4 => cnt <= "100";
WHEN s5 => cnt <= "101";
WHEN s6 => cnt <= "110";
WHEN s7 => cnt <= "111";
END CASE;
END PROCESS;
END one; --end of the architecture
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Notes on code
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Standard VHDL coding style
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An enumeration type for coding of the state
Signals for state and state type
3 processes for modeling
1st process – latching of next_state into state
2nd process – generation of next_state
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Here simple as no control signals
3rd process – generation of output given the state
– a Moore machine.
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The testbench
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ENTITY is blank
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ENTITY testcnt3bit IS
END testcnt3bit;
Declarative region of Arch
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ARCHITECTURE one OF testcnt3bit IS
COMPONENT cnt3bit IS
PORT (clk : IN bit;
cnt : OUT bit_vector(2 downto 0));
END COMPONENT;
FOR all : cnt3bit USE ENTITY work.cnt3bit(one);
-- declare signal for stimulus and response of the DUT
SIGNAL clk : bit;
SIGNAL cnt : bit_vector(2 downto 0);
BEGIN
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In the testbench arch
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BEGIN
-- As tb has clk will never go quiescent
-- set up clk 50% duty cycle 10 ns period
clk <= not clk AFTER 5 ns;
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-- instantiate component
u1 : cnt3bit PORT MAP (clk,cnt);
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END one;
Testbench is very simple – apply the clk and
instantiate the component.
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The VHDL simulation
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Waveform shows binary counting output
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When entered into Quartis
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Automatically did a one-hot encoding
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5 ALUTs – 8 registers – 4 pins
5 total combinational functions
Does a one hot encoding make sense?
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Class discussion
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Compare to a binary encoding
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Code the binary coding straight into VHDL
ENTITY is the same
Declarative region of the ARCHITECTURE
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Declarations are different
ARCHITECTURE two OF cnt3bit IS
SIGNAL state,next_state : bit_vector(2 downto 0);
BEGIN
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And in the processes
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-- latching of next_state
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;
No difference here as both state and next_state
are of the same type. (just bit_vector now)
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Next State Process
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--next_state process
PROCESS (state)
BEGIN
CASE state IS
WHEN “000” => next_state <= “001”;
WHEN “001” => next_state <= “010” ;
WHEN “010” => next_state <= “011” ;
WHEN “011” => next_state <= “100” ;
WHEN “100” => next_state <= “101” ;
WHEN “101” => next_state <= “110” ;
WHEN “110” => next_state <= “111” ;
WHEN “111” => next_state <= “000” ;
END CASE;
END PROCESS;
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Output Process
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For this style the output process is simply
assigning the state to the output as this is a
Moore machine. This can be done with a
concurrent signal assignment statement.
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cnt <= state;
END one;
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Modify the testbench
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In the declarative region add the 2nd arch and cnt for the 2nd arch
(note change in instantiation labels)
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ARCHITECTURE one OF testcnt3bit IS
COMPONENT cnt3bit IS
PORT (clk : IN bit;
cnt : OUT bit_vector(2 downto 0));
END COMPONENT;
FOR u1 : cnt3bit USE ENTITY work.cnt3bit(one);
FOR binenc : cnt3bit USE ENTITY work.cnt3bit(two);
-- declare signal for stimulus and response of the DUT
SIGNAL clk : bit;
SIGNAL cnt,cntbin : bit_vector(2 downto 0);
BEGIN
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After the begin
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BEGIN
-- As tb has clk will never go quiescent
-- set up clk 50% duty cycle 10 ns period
clk <= not clk AFTER 5 ns;
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-- instantiate component
u1 : cnt3bit PORT MAP (clk,cnt);
binenc : cnt3bit PORT MAP (clk,cntbin);
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END one;
Note instantiation of 2nd architecture which has output
cntbin.
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Simulation
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Result from simulation
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Results from Quartis
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Generating the FPGA for cnt3bitbin
This time encoding prevented choice of
one-hot methodology.
Conclusion:
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Tool is not always right!!
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A closer look
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3 F/Fs
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3 LUTs
4 pins
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Controlling the binary assignment
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Being able to control the binary assign results
in more control for the designer and easier
design of other counters.
Can result in more efficient use of FPGA
resources.
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Time for live demo
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Demo of code in Modelsim
Demo of setup in Quartis
Probably want to take note of steps and
editing shortcuts.
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Lecture summary
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HDL from code to simulation
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For the 101 sequence detector
Testbench for the sequence detector
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