CS184a: Computer Architecture (Structures and Organization) Day6: October 11, 2000 Instruction Taxonomy VLSI Scaling Caltech CS184a Fall2000 -- DeHon.
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CS184a: Computer Architecture (Structures and Organization) Day6: October 11, 2000 Instruction Taxonomy VLSI Scaling Caltech CS184a Fall2000 -- DeHon 1 Last Time • Computing requirements • Instruction requirements • Structure Caltech CS184a Fall2000 -- DeHon 2 Today • Instruction Taxonomy • VLSI Scaling Caltech CS184a Fall2000 -- DeHon 3 Instruction Distribution • Beyond 64 PE, instruction bandwidth dictates PE size PEarea 4N =N (648l) PEarea =16Kl2N • Build larger arrays processing elements become less dense Caltech CS184a Fall2000 -- DeHon 4 Instruction Memory Requirements • Idea: put instruction memory in array • Problem: Instruction memory can quickly dominate area, too – Memory Area = 641.2Kl2/instruction – PEarea = 1Ml2 + (Instructions) 80Kl2 Caltech CS184a Fall2000 -- DeHon 5 Instruction Pragmatics • Instruction requirements could dominate array size. • Standard architecture trick: – Look for structure to exploit in “typical computations” Caltech CS184a Fall2000 -- DeHon 6 Two Extremes • SIMD Array (microprocessors) – Instruction/cycle – share instruction across array of PE s – uniform operation in space – operation variance in time Caltech CS184a Fall2000 -- DeHon • FPGA – Instruction/PE – assume temporal locality of instructions (same) – operation variance in space – uniform operations in time 7 Hybrids • VLIW (SuperScalar) – Few pinsts/cycle – Share instruction across w bits • DPGA – Small instruction store / PE Caltech CS184a Fall2000 -- DeHon 8 Architecture Instruction Taxonomy Caltech CS184a Fall2000 -- DeHon 9 Instruction Message • Architectures fall out of: – general model too expensive – look for structure in common problems – exploit structure to reduce resource requirements • Architectures can be viewed in a unified design space Caltech CS184a Fall2000 -- DeHon 10 VLSI Scaling Caltech CS184a Fall2000 -- DeHon 11 Why Care? • In this game, we must be able to predict the future • Rapid technology advance • Reason about changes and trends • re-evaluate prior solutions given technology at time X. Caltech CS184a Fall2000 -- DeHon 12 Why Care • Cannot compare against what competitor does today – but what they can do at time you can ship • Careful not to fall off curve – lose out to someone who can stay on curve Caltech CS184a Fall2000 -- DeHon 13 Scaling • Premise: features scale “uniformly” – everything gets better in a predictable manner • Parameters: l (lambda) -- Mead and Conway (class) – S -- Bohr – 1/k -- Dennard Caltech CS184a Fall2000 -- DeHon 14 Feature Size l is half the minimum feature size in a VLSI process [minimum feature usually channel width] Caltech CS184a Fall2000 -- DeHon 15 Scaling • • • • • Channel Length (L) Channel Width (W) Oxide Thickness (Tox) Doping (Na) Voltage (V) Caltech CS184a Fall2000 -- DeHon 16 Scaling • • • • • Channel Length (L) l Channel Width (W) l Oxide Thickness (Tox) l Doping (Na) 1/l Voltage (V) l Caltech CS184a Fall2000 -- DeHon 17 Effects? • • • • • • • • Area Capacitance Resistance Threshold (Vth) Current (Id) Gate Delay (tgd) Wire Delay (twire) Power Caltech CS184a Fall2000 -- DeHon 18 Area l -> l/k A=L*W A -> A/k2 Caltech CS184a Fall2000 -- DeHon 0.35mm -> 0.25mm • 50% area • 2x capacity same area 19 Area Perspective [2000 tech.] 18mm18mm 0.18mm 60G l2 Caltech CS184a Fall2000 -- DeHon 20 Capacitance • Capacitance per unit area – Cox= eSiO2/Tox – Tox-> Tox/k – Cox -> k Cox Caltech CS184a Fall2000 -- DeHon 21 Capacitance • Gate Capacitance – – – Cgate= A*Cox A -> A/k2 Cox -> k Cox Cgate -> Cgate /k Caltech CS184a Fall2000 -- DeHon 22 Threshold Voltage Caltech CS184a Fall2000 -- DeHon 23 Threshold Voltage • VTH-> VTH /k Caltech CS184a Fall2000 -- DeHon 24 Current • Saturation Current – Id=(mCOX/2)(W/L)(Vgs-VTH)2 – – – – Vgs=V-> V /k VTH-> VTH /k W-> W/k Cox -> k Cox – Id-> Id/k Caltech CS184a Fall2000 -- DeHon 25 Gate Delay tgd=Q/I=(CV)/I • V-> V /k • Id-> Id/k • C -> C /k tgd -> tgd /k Caltech CS184a Fall2000 -- DeHon 26 Resistance • R=rL/(W*t) • W-> W/k • L, t similar • R -> k R Caltech CS184a Fall2000 -- DeHon 27 Wire Delay twire=RLC • R -> k R • C -> C /k • …assuming (logical) wire lengths remain constant... twire -> twire Caltech CS184a Fall2000 -- DeHon 28 Power Dissipation (Static) • Resistive Power – P=V*I – V-> V /k – Id-> Id/k – P-> P /k2 Caltech CS184a Fall2000 -- DeHon 29 Power Dissipation (Dynamic) • Capacitive (Dis)charging • Increase Frequency? – f -> kf ? – P=(1/2)CV2f – V-> V /k – C -> C /k – P -> P/k2 – P-> P/k3 Caltech CS184a Fall2000 -- DeHon 30 Effects? • • • • • • • • Area 1/k2 Capacitance 1/k Resistance k Threshold (Vth) 1/k Current (Id) 1/k Gate Delay (tgd) 1/k Wire Delay (twire) 1 Power 1/k2-> 1/k3 Caltech CS184a Fall2000 -- DeHon 31 Delays? • If delays in gates/switching? • If delays in interconnect? • Logical interconnect lengths? Caltech CS184a Fall2000 -- DeHon 32 Delays? • If delays in gates/switching? – Delay reduce with 1/k [l] Caltech CS184a Fall2000 -- DeHon 33 Delays • Logical capacities growing • Wirelengths? – No locallity->k – Rent’s Rule • L ->n(p-0.5) • [p>0.5] Caltech CS184a Fall2000 -- DeHon 34 Capacity • • • • Rent: IO=C*Np p>0.5 A= C*N2p Logical Area ->k2 k2 A= C*N22p k2 N2p = N22p N2 = k(1/p) N Caltech CS184a Fall2000 -- DeHon • Sanity Check – p=1 – N2 = kN – p~0.5 – N2 ~ k2 N 35 Compute Density • Density = compute / (Area * Time) k3>compute density scaling>k k3: gates dominate, p<0.5 k2: moderate p, good fraction of gate delay k : large p (wires dominate area and delay) Caltech CS184a Fall2000 -- DeHon 36 Power Density • P-> P /k2 (static, or increase frequency) • P-> P/k3 (dynamic, same freq.) A -> A/k2 • P/A -> P/A … or … P/kA Caltech CS184a Fall2000 -- DeHon 37 Physical Limits • Doping? • Features? Caltech CS184a Fall2000 -- DeHon 38 Physical Limits • Depended on – bulk effects • doping • current (many electrons) • mean free path in conductor – localized to conductors • Eventually – single electrons, atoms – distances close enough to allow tunneling Caltech CS184a Fall2000 -- DeHon 39 Finishing Up... Caltech CS184a Fall2000 -- DeHon 40 Big Ideas [MSB Ideas] • Instruction organization induces a design space (taxonomy) for programmable architectures • Moderately predictable VLSI Scaling – unprecedented capacities/capability growth for engineered systems – change – be prepared to exploit – account for in comparing across time Caltech CS184a Fall2000 -- DeHon 41 Big Ideas [MSB-1 Ideas] • Uniform scaling reasonably accurate for past couple of decades • Area increase k2 – Real capacity maybe a little less? • Gate delay decreases (1/k) • Wire delay not decrease, maybe increase • Overall delay decrease less than (1/k) Caltech CS184a Fall2000 -- DeHon 42