Actel A54SX-A and RTSX-SU Reliability Testing Update Antony Wilson, Minal Sawant, and Dan Elftmann.
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Actel A54SX-A and RTSX-SU Reliability Testing Update Antony Wilson, Minal Sawant, and Dan Elftmann S-Antifuses S-antifuses connect the output track of one logic module to the input track of another logic module Cross Antifuse (“X-antifuses”) Logic Module Logic Module Input Antifuses (“I-antifuses”) Logic Module Logic Module Semi-Direct Antifuses (“S-antifuses”) Freeway Antifuses (“F-antifuses”) Single S-antifuse Net Single S-antifuse nets do not use freeways No horizontal or vertical freeway connection Much lower capacitive loading than other types of nets Much faster edge rates and higher peak operational current MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 2 Programming Roadmap (1) UMC Modified Algorithm (UMA) UMA will provide low programming current antifuses longer soaking pulses, in order to ensure no weak links Includes S, B, I and K-antifuses UMA will be included in Silicon Sculptor II Version 3.90 (DOS) / 4.53 (Windows) Shipping since July 2005 UMA uses the new AFM format Introduced in Designer 6.1-SP1 Shipping since March 2005 MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 3 Programming Roadmap (2) S-Antifuse Loading (SAL) Adds capacitive loading by connecting a freeway track Reduces IPEAK in single S-antifuse nets by a minimum of 33% No measurable increase in routing delay of single S-antifuse nets Requires design re-compilation Logic Module Placement will not change, only routing capacitance is added Timing changes are minimal Timing analysis encouraged Logic Module AFM checksum changes SAL Availability Designer / Libero version 6.2-SP1 Shipping since August, 2005 MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 Freeway track adds capacitive loading Single S-Antifuse Net September 7th - 9th, 2005 4 Aerospace Space Qualification Reliability testing to be done by Aerospace Corporation in Space Qualification RTSX72SU-CQ208 RTSX32SU-CQ208 125°C 75-UMA+SAL 150-Standard– Started 5/2/2005 -55°C 75-Standard 150-UMA+SAL Additionally Actel donating 80 A54SX72A-PQ208I units to Aerospace Corp. for testing of SAL & UMA in Long Term Life Experiment (LTLE) Actel donating 80 RTSX72SU-CQ208B units to Aerospace Corp. for testing of SAL & UMA in Long Term Reliability experiment MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 5 High Single S-Antifuse Design Objective Create a reliability test vehicle design that approaches, if not achieves, the maximum number of Single S-Antifuses in a ’72 size device Nets must be capable of being toggled on a Burn In Board (BIB) at a high toggle rate Delay line time should be ~100 ns (short) to reduce thermal influence on measurement MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 6 High Single S-Antifuse Design Combinatorial Circuit(s) Combinatorial (C-Cells) logic utilization to achieve high S-antifuse count S-antifuse used in every routing path between c-cells ccell_in ccell_out(1) ccell1 ccell2 Cluster & Super-Cluster Arrangement CLKA ccell_out(2) Cluster C R C C R C ccell_out(n-1) Super-Cluster ccell_out(n) ccell_in C R C C Timing diagram Device Top C-Cell Routing ccell_in R ccell_in C ccell_out1 C R C C R C delay measurement C R C Single S-Antifuse net segment MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 ccell_out(n) C ccell_out(n-1) R ccell_out2 C ccell_out1 ccell_out1 delay measurement September 7th - 9th, 2005 7 High Single S-Antifuse Design Sequential Circuit(s) Sequential (R_Cells) logic utilization to achieve high S-antifuse count S-antifuse is only on nets routed within a super-cluster Circuit acts like dominoes; CLKB sets up the dominoes and HCLK knocks them down Set R-Cell Routing CLKB HClock rcell_in rcell_out(1) D HCLK SET CLR Q Q1 D Q SET CLR Q Q2 D Q SET CLR Q D Q SET CLR Q Q96 rcell_out(2) D SET CLR Q D Q SET CLR Q D Q SET CLR Q D Q SET CLR C R C C R C C R C C R C C R C C R C Q Q Q rcell_out1 Single S-Antifuse net segment F-X-I Antifuse net segment rcell_out(n-1) D SET CLR Q D Q SET CLR Q D Q SET CLR Q D Q SET CLR Q Timing diagram Q Set rcell_out(n) D SET CLR Q Q D SET CLR Q Q D SET CLR Q Q D SET CLR Q HClock 1st clock edge Qn Q Q1 1 ff time later Q2 2 ff time later Q3 96 ff time later Q96 Delay Measurement MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 8 HiSS A54SX72A-PQ208 Antifuse Utilization B=> I=> S=> K=> 0 987 5007 2033 Antifuse Antifuse Antifuse Antifuse between between between between Local Track and input horizontal segment & input output track & input (semi-direct) input & horizontal NCLK0 or NCLK1, or QCLK 8027 Total Low Programming Current Antifuses F=> X=> V=> H=> W=> G=> 1029 1026 0 0 31 UMA Algorithm applies to all B, I, S & K antifuses All 5,007 S-Antifuses are S-Antifuse nets Antifuse between freeway & output track Single Antifuse between horizontal segment & freeway Antifuse between two vertical tracks Antifuse between two horizontal tracks Antifuse between horizontal segment & 2nd freeway on the net (old-style freeway) 0 Antifuse between output track & 2nd, 3rd, & 4th freeway on the net 2086 Total High Programming Current Antifuses 10113 Total Dynamic Antifuses J=> 45116 Antifuse between input & horizontal NVCC or NGND M=> 46 Antifuse for I/O configuration options Q=> 10 Silicon Signature antifuse in silicon signature words T=> 0 Antifuse between output track & input used early in programming sequence to tie off floating output track Y=> 15769 Antifuse between horizontal segment & vertical NVCC or NGND Z=> 9074 Antifuse between freeway & horizontal NVCC or NGND 70015 Total Static Antifuses 80128 Total Antifuses MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 9 High S-Antifuse Stress Qualification SX72A-PQ208 UMC 24MHz D1JJT1 Experiment STD w/HiSS Designer / Sculptor VCCA TA/TJ (V) (ºC) 6.0 / 3.87 2.50 85/121 T0 110/110 168 Hours 108/108 3rd Read Point 108/108 1000 Hours 108/108 714 hours 6.0 / 3.87 2.50 85/121 132 Due 9/14/05 Due 9/23/05 500 hours Due 10/12/05 Due 11/9/05 STD w/HiSS 6.0 / 3.87 3.00 100/145 99/100 98/99 97/98 813 hours 1 single S-Antifuse 97/97 UMA w/HiSS 6.1 SP1 / 3.90 3.00 100/145 101/101 101/101 100/101 788 hours 1 single S-Antifuse 100/100 UMA w/HiSS+SAL 6.2 SP1 / 3.90 3.00 100/145 102/102 102/102 102/102 651 hours 102/102 STD w/HiSS+SAL 6.2 SP1 / 3.87 108/108 108/108 625 hours 108/108 UMA w/HiSS+SAL 6.2 SP1 / 3.90 3.00 -55/-21 110/110 108/108 108/108 645 hours 108/108 UMA P7 Design 6.1 SP1 / 3.90 2.75 110/145 208/208 204/204 204/204 668 hours 203/203 3.00 100/145 116/117 1 continuity failure 50MHz 3000S MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 108 Due 9/23/05 STD w/HiSS 1 single S-Antifuse 2000 Hours Due 1/4/05 102 Due 9/21/05 Device 59050 not uploaded September 7th - 9th, 2005 10 High S-antifuse Stress Qualification Next Steps Continue 108 HiSS units w/STD algorithm to 2000 hrs VCCA = 2.50 V TA = 85ºC Will add 132 HiSS units w/STD algorithm VCCA = 2.50 V TA = 85ºC Continue 108 HiSS units w/UMA algorithm & SAL to 2000 hrs VCCA = 3.00 V TA = 100ºC MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 11 NASA Test Based on Shape Factor of Aerospace 72SXAU Long Term Experiment S Antifuse NASA Design Weibull 0.01 0.009 0.008 Percent Failure 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 1 10 100 1000 10000 100000 Hours MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 12 S Antifuse FIT CALC for NASA 32S Test 0.0091 in 100K Hours = 91 FIT 5X for 0.2eV TJ = 150ºC 10X for Voltage Acceleration VCCA = 2.75 V 2X for Utilization Single S-Antifuse utilization 251 vs. 832 5X for Visibility If delay >10ns no visibility factor FITs = 91/500 = .182 FIT in 10 Years MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 13 B-Antifuse within the Device Architecture The B-Antifuse is driven by the dedicated DB-Inverter in each C-Cell 4,126 unique functions exist in the RTSX-SU library I3277 Macro Implementation DBInverter 3,730 of these macro library configurations utilize BAntifuses D3 3 2 D2 1 D1 1 0 1 Y D0 1 0 Y 0 0 0 X X X 1 0 0 1 X X X 0 0 1 X 0 X X 0 0 1 X 1 X X 1 1 0 X X 0 X 0 1 0 X X 1 X 1 1 0 X X X 0 0 1 0 X X X 1 1 0 A0 S0 16,879 different configurations S0 S1 D0 D1 D2 D3 No output resistor 0 S1 B0 A1 D0 0 D1 1 D2 2 D3 3 Y B1 S0 Six B-Antifuses available per C-Cell driven by DB-Inverter S1 Un-programmed Antifuse (no connection) Programmed Antifuse (connection) 3,001 Macros have single B-Antifuse configurations 2,565 have no other option XOR3 Macro Implementation Example DBInverter No output resistor C D3 C D2 337 Can be implemented without the B-Antifuse map string configurations 99 have a multiple B-Antifuse map string option for macro implementation 0 1 Y D1 D0 C 1 0 B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 0 A0 B None of the 3,730 have a don’t care input available for additional loading 1 A A B0 A B C Y A1 A B1 Six B-Antifuses available per C-Cell driven by DB-Inverter B =1 Y C Un-programmed Antifuse (no connection) Programmed Antifuse (connection) MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 14 B-Antifuse Usage Statistics Number of Single B-Antifuse Nets vs. Aerospace ASQ '32 Customer Designs Raw Average -> 302 Raw Geometric Mean -> 222 Min -> 15 Max -> 572 3.7 5.1 75.2 2.0 '72 Customer Designs Raw Average -> 673 Raw Geometric Mean -> 637 Min -> 314 Max -> 1,172 4.8 5.1 10.3 2.8 All Customer Designs Normalized Average -> 645 5.0 Normalized Geometric Mean -> 527 Reliability Test Vehicle (RTV) Designs RT54SX32SU-CQ208 ASQ 1,128 RT54SX32SU-CQ208 Colonel 35 RT54SX32SU-CQ208 General 21 RT54SX32SU-CQ208 NASA 29 RT54SX72SU-CQ208 ASQ RT54SX72SU-CQ256 QBI RT54SX72SU-CQ208 P7 A54SX72A-PQ208 QBI A54SX72A-PQ208 P7 A54SX72A-PQ208 ALTE A54SX72A-PQ208 HiSS MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update 3,232 1,241 23 1,164 28 40 Paper #1028 6.1 1.0 32.2 53.7 38.9 1.0 2.6 140.5 2.8 115.4 80.8 n/a September 7th - 9th, 2005 15 HiBS Design Concept Maximize B-Antifuse utilization using CM8INV macros Maximize S-Antifuse utilization by routing c-cells in serial chain within supercluster S-Antifuse ccell_in I-Antifuse B-Antifuse '1' '0' '0' B-Antifuse '1' 0 1 2 3 CLKA '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' ccell_out[1] 0 1 2 3 S-Antifuse I-Antifuse B-Antifuse '1' '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' ccell_out[2] 0 1 2 3 S-Antifuse I-Antifuse B-Antifuse '1' '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' ccell_out[N-1] 0 1 2 3 S-Antifuse I-Antifuse B-Antifuse '1' '0' '0' B-Antifuse '1' 0 1 2 3 MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update '0' '0' B-Antifuse '1' 0 1 2 3 '0' '0' 0 1 2 3 Paper #1028 B-Antifuse '1' '0' '0' 0 1 2 3 ccell_out[N] September 7th - 9th, 2005 16 HiBS Routing within a supercluster to maximize S-Antifuse utilization C-Cell Routing S-Antifuse ccell_in Basic R and C Cells FXI-Antifuses C R C C R C C R C C R C C R C C R C Cluster C R C C R C Super-Cluster ccell_out1 Routing technique on a device Device Top ccell_out(n) ccell_out(n-1) ccell_out2 ccell_out1 ccell_in MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 17 HiBS A54SX72A-PQ208 Antifuse Utilization B=> 4900 Antifuse between Local Track and input S=> 2248 Antifuse between output track & input(semi-direct) I=> 1755 Antifuse between horizontal segment & input K=> 21 Antifuse between input & horizontal NCLK0 or NCLK1, or QCLK 8924 Low Programming Current Dynamic Antifuses Antifuse between freeway & output track UMA Algorithm applies to all B, I, S & K antifuses All 4,900 B-Antifuses are Single B-Antifuse nets F=> 4024 G=> 0 Antifuse between output track & 2nd, 3rd, & 4th freeway on the net H=> 0 Antifuse between two horizontal tracks V=> 0 Antifuse between two vertical tracks W=> 15 X=> 1774 Antifuse between horizontal segment & freeway 5813 High Programming Current Dynamic Antifuses Antifuse between horiz segment & 2nd freeway on the net (old-style freeway) 14737 Total Dynamic Antifuses J=> 44219 Antifuse between input & horizontal NVCC or NGND M=> 24 Antifuse for I/O configuration options Q=> 11 Silicon Signature afuse in silicon signature words Y=> 15021 Antifuse between horizontal segment & vertical NVCC or NGND Z=> Antifuse between freeway & horizontal NVCC or NGND 6095 65370 Total Static Antifuses 80107 Total Antifuses MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 18 High B-Antifuse Stress Experiments A54SX72A-PQ208 UMC 24 MHz Expt Vcca (V) TA/TJ (ºC) T0 160h 500h 1000h 2000h UMA w/HiBS + SAL 2.5 105/145 108/108 108/108 9/28/05 10/19/05 12/7/05 UMA w/HiBS + SAL 3.0 95/145 108/108 108/108 9/28/05 10/19/05 12/7/05 UMA w/HiBS + SAL 3.25 83/145 108/108 9/10/05 9/28/05 10/19/05 12/7/05 MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 19 Aerospace Space Qualification Based on Shape Factor of A54SX72A (UMC) Aerospace Long Term Experiment (ALTE) B Antifuse ASQ Design Weibull 0.04 0.035 0.03 Percent Failure 0.025 0.02 0.015 0.01 0.005 0 1 10 1000 100 10000 100000 Hours MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 20 B-Antifuse FIT CALC for 32S Aerospace Space Qualification 0.0307 to 0.0458 in 100K Hours = 307 - 458 FIT 50 – 60% Confidence 5X for 0.2eV Tj = 150ºC 5X for Utilization Single B-Antifuse utilization 645 vs 3232 2.5X for Visibility 5X < 10ns 1X > 10ns FITs = 307 to 458 / 67.5 = 4.6 to 6.8 FIT in 10 Years MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 21 Aerospace Space Qualification MAPLD 2005: Actel A54SX-A and RTSX-SU Reliability Testing Update Paper #1028 September 7th - 9th, 2005 22