Transcript System-Level Living Roadmap GSRC Annual Symposium September 28 & 29, 2006 Faculty: Kahng, Markov, Orshansky, Sylvester.

System-Level Living Roadmap
GSRC Annual Symposium
September 28 & 29, 2006
Faculty: Kahng, Markov, Orshansky, Sylvester
System-Level Living Roadmap
• Only cost-effective technology innovations reach production
– What are relevant bounds, and how do they evolve?
– What are quantified benefits from available technology options?
– Beyond-ITRS: what are system implementation roadblocks?
• System-level design optimization and scaling
– What are the relevant models and metrics for system scaling?
• Early analysis tools
– Map technology concerns (power, variability, speed, area, …) to
system concerns (total cost, availability, …)
• Roadmaps
– Connect applications to design and process technologies
 well-calibrated cost and resource tradeoffs
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Roadmap of Parametric Yield Estimation and
Optimization: TUNES
Variability Data
Technology / Circuit Data
Fmax Variability
Statistical Clock Skew
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GSRC Annual Symposium
SER Macromodeling
3
Roadmap of Parametric Yield Estimation and Optimization:
Block-Level Probabilistic Power-Delay Exploration
• Variability greatly impacts leakage
power and parametric yield
– Exponential dependency on process
•
Package often sets power limits
– Cooling costs grow rapidly for higher power
Cooling/Power Limit
Leakage
Power
Number of Parts
Power w/
Leakage
Fast
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Switching
Power
Minimum Ship
Frequency
Design Spread
Max Ship Freq
(No Leakage)
Max Ship Freq
(With Leakage)
GSRC Annual Symposium
Slow
4
Roadmap of Parametric Yield Estimation and Optimization:
Block-Level Probabilistic Power-Delay Exploration
– Efficient, large-scale parametric yield
maximization
• Designer chooses sweet spot in power-delay
space, trades timing yield for power yield, etc.
– E.g., 5% timing yield loss  25% less power
200
900
800
750
700
650
400
600
Deterministic optimization
Statistical: inter and intra-chip variation
Statistical: all intra-chip variation
850
Total Power (W)
99.9% Power (W)
850
0
Static Power ( μW )
Timing yield = 99.9%
Timing yield = 95%
Timing yield = 84%
900
Statistical Optimization
Deterministic Optimization
Frequency
• How much parametric yield loss can be
recovered?
• DAC-05 Best Paper: Robust LP, second-order
conic programming for sizing / dual Vth
800
750
700
650
600
600
550
0.60
0.53
0.56
0.58
0.60
0.62
0.64
0.67
0.61
0.62
0.63
0.64
0.66
0.67
Delay (ns)
Delay (ns)
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Roadmap of Reliability: Impact of Dynamic
Reliability Management
• TDDB, EM, thermal cycling, NBTI with dynamic stress inputs
• PID + threshold control solution
• DRM voltage control
– Boosts/throttles maximum assignable voltage
– +25% peak performance with typical workload/temperature
• +12-15% peak performance  workloads
• +10-12% peak performance  temperature
• Future directions
– Parametric performance
degradations vs. hard failures
– Sensor architecture and
placement
– ElastIC: A system-level
adaptive architecture
1.8
1.6
“Boost”
1.4
VDD
1.2
1
0.8
0.6
0
2
4
6
8
In a DRM System, the maximum voltage can be
“boosted” to allow periods of higher peak
x 10
performance
while maintaining a margin below
3
the budgeted damage curve.
10
12
x 10
4
-9
2.5
Lifetime Budget Curve
2
Damage
1.5
DRM Damage Curve
1
0.5
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DVS Damage Curve
0
GSRC Annual Symposium
0
2
4
6
Time
8
10
12
x 10 4
6
Roadmap of Reliability: Efficient Soft Error
Analysis and Optimization in Combinational Logic
• Proposed algorithm considers injection, propagation, and merging of
SET descriptors (capturing correlation between transient waveforms and
rate distribution function) in STA-like fashion
– Waveform models based on Weibull, 1-time characterization cost
• Highly efficient: runtime linear with #gates (25K gates in 0.2sec)
• Accurate: ~15% error in FIT
•
vs. Monte-Carlo SPICE
Q0  {Q1, Q2, …, Qm}
– Runtime: 1 min
for 5K gates
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R1
Rate R
• Gate sizing + flip-flop
assignment shows 28X
SER reduction with no
delay penalty and 5%
area overhead
Rate Function
Transient Injection
R2
Voltage (V)
• Used in SER optimization
Qm
Q1
Rm
Q1 Q2
Charge Q
Time (ps)
Qm
SET Descriptor
(d0,d1)
Vector b
Vector R
GSRC Annual Symposium
Waveform Parameters
7
Roadmap of Reliability: Bottom-Up Reliability
Prediction
• Pulse Generation:
• System-level analysis requires:
– Precise gate electrical
properties
– Logical structure of the circuit
– System-level timing behavior
–  Electrical, logical, and timing
window masking
• Cell library characterization
• Intractability (#P) of logical
masking
– Library: Output Waveform =
f(Collected Charge)
CL
A=0
Library
•
Pulse Propagation:
– Library: Output Waveform =
f(Input Waveform)
• Three new static SER analysis
tools
Y
0
PWin
Vth
PW
B=1
– Pioneered use of decision
diagrams in this context
– DATE-05 Best Paper award
Vth
0
Y
Vth
Library
CL
A
B=1
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Roadmap of Reliability: Fast Analysis of Soft Error
Susceptibility (FASER) for Cell-Based Designs
Fast analytical modeling and
computational technique for logic SER
analysis for cell level designs
0.02
Error Probability
•
– Excellent accuracy compared to
SPICE
– Best Paper Award, ISQED 2006
SPICE
FASER
0.01
0
C1
0.6
C3
C4
C5
Benchmark Circuit
C6
C7
With Logic Masking
Without Logic Masking
0.5
Soft Error Rates (a.u.)
C2
0.4
0.3
0.2
0.1
0
1
2
3
4
5
6
7
Logic Depth
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Roadmap of Reliability: System Susceptibility to
Soft Errors: Memory Modeling
•
•
Memory arrays much more sensitive
to single event upsets
Developed first analytical model for
predicting SER noise margins under
dynamic disturbances (single event
upsets)
Inverter 1
Iseu
V2
V1
C
C
Inverter 2
0.8
Analyitcal
In (mA)
0.6
SPICE
Bounds
0.4
0.2
I snm
0
0
20
40
60
Tcrit (ps)
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Roadmap of Reliability: Synthesis for Reliability
and Probabilistic Testing
• Optimize reliability using
recent competitive
synthesis frameworks
– Allow or veto logic
transformations
– Using ABC from Berkeley
New project with
Air Force Research Lab
• Evaluating 4 GSRC
reliability evaluators
and two more
– Figure out which work !
• Use in estimation
– Take deterministic patterns • Use in synthesis
and optimization
– Compute multiplicities
using a reliability evaluator • Use in circuit test
• Probabilistic test
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Roadmap of Power and Variability: Energy-Optimal
Gate Sizing for Subthreshold Circuits
• Subthreshold energy efficiency is limited by leakage
– Energy optimal supply voltage, Vmin, determined by rise in leakage
– At Vmin, leakage accounts for ~30% of total energy
E  E dyn  E leak  C  Vdd2    Ileak  Vdd  TCLK
Number of Paths
700
600
500
400
300
200
100
0
Number
NumberofofPaths
Paths
0.4
0.6
0.8
c7552
c499
Before
300
500
400
200
300
500
400
300
200
100
After
0
0.2
Delay
0.4
c7552
(Normalized
September
28, 2006
300
Before
0.6
0.0
0.2
0.4
0.6
0.8
1.0
c7552
After
6% energy
reduction
200
100
100
200
600
1.0
Before
0.0
r of Paths
0.2
700
400
600
400
700
0
0.0
0.8
to TCLK)
After
1.0
Number of Paths
Number of Paths
• Increasing gate sizes along critical paths can reduce energy
– Shorter clock period = shorter leakage time
– A reduction c499
in leakage affects the location of c499
Vmin; therefore, Vdd can
After
After
Before
Before
be
reduced
if
leakage
is
reduced

• An energy-driven, TILOS-like sizing algorithm yields energy savings of
~6-15% on ISCAS85 benchmarks
400
After
300
Before
15% energy
reduction
200
100
0
0.0
0.2
0.4
0.6
0.8
1.0
Delay (Normalized to TCLK)
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Roadmap of Power and Variability: Design Assessment
under Realistically Available Uncertainty Descriptions
• In practice, detailed process
characterization data for current and
future generations are not available
E [X ] V ar [X ]
– Only partial probabilistic descriptions
are accessible, e.g., mean and
variance
– Timing, power, and parametric yield
estimates are affected
C um ulative P robability
• Probabilistically-enhanced interval
analysis
– Use mean, variance, and intervals
of circuit parameters to estimate
probabilistic bounds for timing and
power
– Probability box: bounds for
cumulative distribution function
X
X
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
 Vdd (V)
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Roadmap of Power and Variability:
Intra-Gate Biasing
• Exploit edge effects in modern MOSFET devices that lead to
different Ion/Ioff current densities based on position in
channel
• Key: lengthen channel near edges to suppress high leakage
there, reduce Ldrawn in center slightly to compensate
• FREE circuit-level leakage reduction on the order of 5-6%
– No delay penalty or optimization cost
• An orthogonal knob to all other
circuit optimization techniques
Leakage Improvement (%)
14
Leakage Improvement vs Width
12
10
8
6
4
2
200
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400
600
Width (nm)
800
1000
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Roadmap of Cost: Low-Volume Implementation
• What can be recovered along cost trajectory of Moore’s Law?
– OPC, reticle plan, multi-layer reticle strategy, multi-flow production strategy,
wafer shot map, blading, mask write and inspect, dicing plan, …
 many optimization opportunities
– Goal: 10X reduction in per-die cost for low volume
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MFMLMP Reticles
• A reticle has multi-layers of multi-projects of multi-flows
• Different printing frames for different wafers
• More design challenges: layer assignment, flow embedding and
frame floorplan
Die 1
Lay 3
Die 2
Lay 3
Die 1
Lay 3
Die 2
Lay 3
Die 1
Lay 3
Die 2
Lay 3
Reticle 1
Die 1
Lay 2
Die 1
Lay 2
Frame
Die 2
Lay 2
Die 1
Lay 1
Die 1
Reticle 2
Die 1
Lay 1
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Die 2
Lay 1
Wafer 1
Die 2
Lay 2
Die 2
Lay 1
Die 2
Die 1
Lay 1
Die 2
Lay 1
Die 1
Die 2
Wafer 2
Example of MFMLMP Reticles: Layer 2 of Die 1
and Die 2 cannot share the same reticle
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GSRC On-Line MFMLMPR Designer
•
•
•
•
Flexible: Handles all known practical design constraints
Fast: Interactive solver to minimize manufacturing costs
Graphical viewing of output
Co-developed with, used at Cypress Semiconductor for MFMLMP Reticle design
Define Parameters
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Input Data
GSRC Annual Symposium
Output
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Roadmap for Physical Implementation QOR
• Delay, Power: large part in interconnect
– Growing problem with every technology node
– Spatial embedding becomes more critical
– Unpleasant surprises at first spatial
embedding
(industry: many RTL designs are found
infeasible)
• Early planning for distances, shapes and
sizes
– Manual planning has hit the complexity limit
– System must co-evolve with its spatial
embedding
– Embedded memories, IPs, analog/RF, …
• Vertically-consistent spatial embedding
– Consistent objectives and optimizations
through multiple levels of abstraction
– Smooth transitions between design steps,
with gradual refinement
– Support for design optimizations such as
high-level and RTL synthesis
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Vertical Consistency (1)
•
SCAMPI: SCalable Advanced Macro Placement
Improvements
– Variety of macro sizes & shapes
– Look-ahead, macro clustering,
obstacle evasion
•
Floorist:
Floorplan Assistant
(constraint-driven FP repair)
red: overlap
September 28, 2006
blue: block
movement
(no overlap)
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Vertical Consistency (2)
•
•
Physically safe logic restructuring
Top-down whitespace & buffer area allocation
•
Support for design optimizations
via selective re-embedding (below)
More direct optimization of routed net lengths
several design steps
•
(ROOSTER), at
Legalize
Improve
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SLLR Theme Posters
•
Parametric Yield Estimation and Optimization
–
–
–
•
Roadmap of Reliability
–
–
–
•
•
•
Eric Karl, Dennis Sylvester and David Blaauw: Multi-Mechanism Reliability Modeling and
Management in Dynamic Microprocessor-Based Systems
Scott Hanson, Dennis Sylvester and David Blaauw: A New Technique For Jointly Optimizing Gate
Sizing and Supply Voltage in Ultra-Low Energy Circuits
Saumil Shah, Dennis Sylvester, Andrew Kahng and Youngmin Kim: Intra-Gate Channel Length
Biasing for Transistor-Level Circuit Optimization
Bin Zhang and Michael Orshansky: Evaluating Reliability of On-Chip SRAM Arrays using Dynamic
Stability Analysis
Rajeev Rao, Vivek Joshi, David Blaauw and Dennis Sylvester: Efficient Soft Error Rate
Computation and Circuit Optimization Techniques to Mitigate Soft Errors in Combinational Logic
Wei-Shen Wang and Michael Orshansky: Yield Estimation under Realistic Descriptions of
Parameter Uncertainty
Roadmap of Cost
–
Andrew Kahng and Xu Xu: A General Framework for Multi-Flow Multi-Layer Multi-Project Reticle
Design
Roadmap of Physical Implementation QOR
–
Jarrod Roy and Igor Markov: Vertically-Consistent Spatial Embedding of Integrated Circuits and
Systems
Roadmap of Power and Variability
–
Andrew Kahng, Swamy Muddu and Chul-Hong Park: A Scalable Auxiliary Pattern-Based OPC
Strategy for Better Printability, Timing and Leakage Control
– Andrew Kahng and Swamy Muddu: Design-Centric Modeling and Optimization of BEOL
Interconnect Stacks
– Andrew Kahng, Kambiz Samadi and Puneet Sharma: Study of Floating Fill on Interconnect
Capacitance
– Andrew Kahng and Kambiz Samadi: Nanometer Era CMP Fill for Variability Reduction
– Andrew Kahng and Puneet Sharma: CMP Fill for Reduced STI Variability
– Andrew Kahng and Swamy Muddu: Predictive Modeling of Systematic Intra-die Variability
September
28, 2006
GSRCOptimization
Annual Symposium
– Andrew
Kahng and Rasit Topaloglu: Interconnect
through Design Rule Generation
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Toward System Scaling Theory
Traditional Scaling
• Driven by min feature size
Future Scaling
• Driven by system constraints
• Non-determinism: size impact
• Determinism: size directly
mediated by power density,
impacts performance and density
redundancy overhead, low yield,
increased comm overhead
• System-level overdesign and
effective transistor density
• FO4-based performance metric
• Transistors are either logic or
memory
• Cost not discussed (e.g., design
TAT, leakage current from Tox
scaling, …)
September 28, 2006
• Performance is achieved by multicore architectures running at lower
frequencies
• Adaptivity/reliability  many
transistors are used to diagnose and
tune
• Power trades off with design time
• Impacts of concurrency, spatial
embedding, application domain, …
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Future: GSRC Modeling and Metrics SIG
• Enable system design to comprehend impact and feasibility of
technology options
– Variability, power, cost
– Reliability, flexibility, resilience
• Initial focus: uncalibrated, “variational” scaling models
– Priority: modeling requests from system-level design and GSRC
sponsors
– “X% increase in reliability requires Y% increase in power”?
– “X% (transient + hard) fault coverage can be achieved with < Y% area
overhead”?
– How to measure efficiency and yield in the presence of failures?
– Approximations + Abstractions  “block models” for system optimization
• Future system scaling is dominated by silicon non-idealities
– Variability and reliability will fundamentally change density, power,
speed, cost scaling laws
– Long-term goal: a new system scaling theory
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