Transcript Lecture 14 Xilinx FPGA Memories ECE 448 – FPGA and ASIC Design with VHDL.

Lecture 14
Xilinx FPGA Memories
ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 11, Xilinx Spartan-3 Specific Memory
ECE 448 – FPGA and ASIC Design with VHDL
2
Recommended reading
• XAPP463 Using Block RAM in Spartan-3 Generation FPGAs
Google search: XAPP463
• XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3
Generation FPGAs
Google search: XAPP464
• XST User Guide, Section: Coding Techniques
Google search: XST User Guide (PDF)
http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.html (HTML)
• ISE In-Depth Tutorial, Section: Creating a CORE Generator Module
Google search: ISE In-Depth Tutorial
ECE 448 – FPGA and ASIC Design with VHDL
3
Memory Types
4
Memory Types
Memory
RAM
ROM
Memory
Single port
Dual port
Memory
With asynchronous
read
With synchronous
read
5
Memory Types
Memory
Distributed
(MLUT-based)
Block RAM-based
(BRAM-based)
Memory
Inferred
Instantiated
Manually
Using Core Generator
6
FPGA Distributed
Memory
7
CLB Slice
COUT
YB
G4
G3
G2
G1
Y
Look-Up
O
Table
D
Carry
&
Control
Logic
S
Q
CK
EC
R
F5IN
BY
SR
XB
F4
F3
F2
F1
CIN
CLK
CE
X
Look-Up
Table O
Carry
&
Control
Logic
S
D
Q
CK
EC
R
SLICE
8
Xilinx Multipurpose LUT
16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
9
Distributed RAM
RAM16X1S
• CLB LUT configurable as
Distributed RAM
=
LUT
• An LUT equals 16x1 RAM
• Cascade LUTs to increase RAM size
D
WE
WCLK
A0
A1
A2
A3
A4
LUT
=
• Two LUTs can make
• 32 x 1 single-port RAM
• 16 x 2 single-port RAM
• 16 x 1 dual-port RAM
O
RAM32X1S
• Synchronous write
• Asynchronous read
• Can create a synchronous read by
using extra flip-flops
• Naturally, distributed RAM read is
asynchronous
D
WE
WCLK
A0
A1
A2
A3
LUT
or
O
RAM16X2S
D0
D1
WE
WCLK
A0
A1
A2
A3
O0
O1
or
RAM16X1D
D
WE
WCLK
A0
SPO
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
10
FPGA Block RAM
11
Block RAM
Port B
Port A
Spartan-3
Dual-Port
Block RAM
Block RAM
• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 104 memory blocks
• 18 kbits = 18,432 bits per block (16 k without parity bits)
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs
• Synchronous write and read (different from distributed RAM)
12
RAM Blocks and Multipliers in Xilinx FPGAs
RAM blocks
Multipliers
Logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
13
Spartan-3 Block RAM Amounts
14
Block RAM can have various configurations (port
aspect ratios)
1
2
0
4
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
8+1
0
2k x (8+1)
2047
16+2
0
1023
1024 x (16+2)
16,383
15
Block RAM Port Aspect Ratios
16
Single-Port Block RAM
DO[w-p-1:0]
DI[w-p-1:0]
17
Dual-Port Block RAM
DOA[wA-pA-1:0]
DIA[wA-pA-1:0]
DOA[wB-pB-1:0]
DIB[wB-pB-1:0]
18
Dual-Port Bus Flexibility
RAMB4_S18_S9
WEA
Port A In
1K-Bit Depth
ENA
RSTA
DOA[17:0]
Port A Out
18-Bit Width
DOB[8:0]
Port B Out
9-Bit Width
CLKA
ADDRA[9:0]
DIA[17:0]
WEB
ENB
Port B In
2k-Bit Depth
RSTB
CLKB
ADDRB[10:0]
DIB[8:0]
• Each port can be configured with a different data bus width
• Provides easy data width conversion without any additional logic
19
Two Independent Single-Port RAMs
RAMB4_S1_S1
Port A In
8K-Bit Depth
0, ADDR[12:0]
WEA
ENA
RSTA
DOA[0]
Port A Out
1-Bit Width
CLKA
ADDRA[12:0]
DIA[0]
Port B In
8K-Bit Depth
1, ADDR[12:0]
WEB
ENB
RSTB
DOB[0]
Port B Out
1-Bit Width
CLKB
ADDRB[12:0]
DIB[0]
•
Added advantage of True Dual-Port
•
•
No wasted RAM Bits
Can split a Dual-Port 16K RAM into two
Single-Port 8K RAM
•
Simultaneous independent access to each
RAM
•
To access the lower RAM
• Tie the MSB address bit to Logic Low
•
To access the upper RAM
• Tie the MSB address bit to Logic
High
20
Inference
vs.
Instantiation
21
22
Generic
Inferred
RAM
23
Distributed versus Block RAM Inference
Examples:
1.
Distributed RAM with asynchronous read
2.
Distributed RAM with "false" synchronous read
3.
Block RAM with synchronous read
4.
Distributed dual-port RAM with asynchronous read
More excellent RAM examples from XST Coding Guidelines:
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode.html
(Click on RAMs)
24
Distributed RAM with asynchronous read
25
Distributed RAM with asynchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raminfr is
generic ( bits : integer := 32;
-- number of bits per RAM word
addr_bits : integer := 3);
-- 2^addr_bits = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
a
: in std_logic_vector(addr_bits-1 downto 0);
di : in std_logic_vector(bits-1 downto 0);
do : out std_logic_vector(bits-1 downto 0));
end raminfr;
26
Distributed RAM with asynchronous read
architecture behavioral of raminfr is
type ram_type is array (2**addr_bits-1 downto 0)
of std_logic_vector (bits-1 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(unsigned(a))) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(unsigned(a)));
end behavioral;
27
Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-5
Cell usage:
GND
1 use
RAM16X4S
8 uses
I/O ports: 69
I/O primitives: 68
IBUF
36 uses
OBUF
32 uses
BUFGP
1 use
I/O Register bits:
0
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Single Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 32 (2%)
28
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of occupied Slices:
16 out of 768 2%
Number of Slices containing only related logic: 16 out of 16 100%
Number of Slices containing unrelated logic:
0 out of 16 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:
32 out of 1,536 2%
Number used as 16x1 RAMs:
32
Number of bonded IOBs:
69 out of 124 55%
Number of GCLKs:
1 out of
8 12%
29
Distributed RAM with "false" synchronous read
30
Distributed RAM with "false" synchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity raminfr is
generic ( bits : integer := 32;
-- number of bits per RAM word
addr_bits : integer := 3);
-- 2^addr_bits = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
a
: in std_logic_vector(addr_bits-1 downto 0);
di : in std_logic_vector(bits-1 downto 0);
do : out std_logic_vector(bits-1 downto 0));
end raminfr;
31
Distributed RAM with "false" synchronous read
architecture behavioral of raminfr is
type ram_type is array (2**addr_bits-1 downto 0)
of std_logic_vector (bits-1 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(unsigned(a))) <= di;
end if;
do <= RAM(conv_integer(unsigned(a)));
end if;
end process;
end behavioral;
32
Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-5
Cell usage:
FD
32 uses
GND
1 use
RAM16X4S
8 uses
I/O ports: 69
I/O primitives: 68
IBUF
36 uses
OBUF
32 uses
BUFGP
1 use
I/O Register bits:
0
Register bits not including I/Os: 32 (2%)
RAM/ROM usage summary
Single Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 32 (2%)
33
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops:
32 out of 1,536 2%
Logic Distribution:
Number of occupied Slices:
16 out of 768 2%
Number of Slices containing only related logic: 16 out of 16 100%
Number of Slices containing unrelated logic:
0 out of 16 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:
32 out of 1,536 2%
Number used as 16x1 RAMs:
32
Number of bonded IOBs:
69 out of 124 55%
Number of GCLKs:
1 out of
8 12%
Total equivalent gate count for design: 4,355
34
Block RAM with synchronous read (read through)
35
Block RAM with synchronous read (read through)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
library synplify; -- XST does not need this
entity raminfr is
generic ( bits : integer := 32;
-- number of bits per RAM word
addr_bits : integer := 3);
-- 2^addr_bits = number of words in RAM
port (clk : in std_logic;
we : in std_logic;
a
: in std_logic_vector(addr_bits-1 downto 0);
di : in std_logic_vector(bits-1 downto 0);
do : out std_logic_vector(bits-1 downto 0));
end raminfr;
36
Block RAM with synchronous read (read through)
cont'd
architecture behavioral of raminfr is
type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector
(bits-1 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector(addr_bits-1 downto 0);
attribute syn_ramstyle : string; -- XST does not need this
attribute syn_ramstyle of RAM : signal is "block_ram";
-- XST does not need this
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(unsigned(a))) <= di;
end if;
read_a <= a;
end if;
end process;
do <= RAM(conv_integer(unsigned(read_a)));
end behavioral;
37
Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-5
Cell usage:
GND
1 use
RAMB16_S36 1 use
VCC
1 use
I/O ports: 69
I/O primitives: 68
IBUF
36 uses
OBUF
32 uses
BUFGP
1 use
I/O Register bits:
0
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Block Rams : 1 of 4 (25%)
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 0 (0%)
38
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic:
0 out of
0 0%
Number of Slices containing unrelated logic:
0 out of
0 0%
*See NOTES below for an explanation of the effects of unrelated logic
Number of bonded IOBs:
69 out of 124 55%
Number of Block RAMs:
1 out of
4 25%
Number of GCLKs:
1 out of
8 12%
39
Distributed dual-port RAM with asynchronous read
40
Distributed dual-port RAM with asynchronous read
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity raminfr is
generic ( bits : integer := 32;
-- number of bits per RAM word
addr_bits : integer := 3);
-- 2^addr_bits = number of words in RAM
port (clk : in std_logic;
we
: in std_logic;
a
: in std_logic_vector(addr_bits-1 downto 0);
dpra : in std_logic_vector(addr_bits-1 downto 0);
di
: in std_logic_vector(bits-1 downto 0);
spo : out std_logic_vector(bits-1 downto 0);
dpo : out std_logic_vector(bits-1 downto 0));
end raminfr;
41
Distributed dual-port RAM with asynchronous read
architecture syn of raminfr is
type ram_type is array (2**addr_bits-1 downto 0) of
std_logic_vector (bits-1 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(unsigned(a))) <= di;
end if;
end if;
end process;
spo <= RAM(conv_integer(unsigned(a)));
dpo <= RAM(conv_integer(unsigned(dpra)));
end syn;
42
Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-5
Cell usage:
GND
1 use
I/O ports: 104
I/O primitives: 103
IBUF
39 uses
OBUF
64 uses
BUFGP
1 use
I/O Register bits:
0
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 32
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 64 (4%)
43
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of occupied Slices:
32 out of 768 4%
Number of Slices containing only related logic: 32 out of 32 100%
Number of Slices containing unrelated logic:
0 out of 32 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:
64 out of 1,536 4%
Number used for Dual Port RAMs:
64
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs:
104 out of 124 83%
Number of GCLKs:
1 out of
8 12%
44
Specification of memory types recognized
by Synplify Pro
SIGNAL memory : vector_array;
Block RAM Memory:
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is "block_ram";
LUT-based Distributed Memory:
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is “select_ram";
45
Generic
Inferred
ROM
46
Distributed dual-port RAM with asynchronous read
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity rominfr is
generic ( bits : integer := 10;
-- number of bits per ROM word
addr_bits : integer := 3);
-- 2^addr_bits = number of words in ROM
port (a
: in std_logic_vector(addr_bits-1 downto 0);
do : out std_logic_vector(bits-1 downto 0));
end rominfr;
47
Distributed dual-port RAM with asynchronous read
architecture behavioral of rominfr is
type rom_type is array (2**addr_bits-1 downto 0)
of std_logic_vector (bits-1 downto 0);
constant ROM : rom_type :=
("0000110001",
"0100110100",
"0100110110",
"0110110000",
"0000111100",
"0111110101",
"0100110100",
"1111100111");
begin
do <= ROM(conv_integer(unsigned(a)));
end behavioral;
48
Report from Synthesis
Resource Usage Report for rominfr
Mapping to part: xc3s50pq208-5
Cell usage:
VCC
1 use
LUT2
2 uses
LUT3
7 uses
I/O ports: 13
I/O primitives: 13
IBUF
3 uses
OBUF
10 uses
I/O Register bits:
0
Register bits not including I/Os: 0 (0%)
Mapping Summary:
Total LUTs: 9 (0%)
49
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs:
9 out of 1,536 1%
Logic Distribution:
Number of occupied Slices:
5 out of 768 1%
Number of Slices containing only related logic:
5 out of
5 100%
Number of Slices containing unrelated logic:
0 out of
5 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:
9 out of 1,536 1%
Number of bonded IOBs:
13 out of 124 10%
50
FPGA
specific memories
(Instantiation)
51
RAM 16x1 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity RAM_16X1_DISTRIBUTED is
port(
CLK : in STD_LOGIC;
WE : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_IN : in STD_LOGIC;
DATA_OUT : out STD_LOGIC
);
end RAM_16X1_DISTRIBUTED;
52
RAM 16x1 (2)
architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of
RAM_16X1_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro, only;
-- ignored during simulation
attribute INIT : string;
attribute INIT of RAM_16x1s_1: label is "0000”;
component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic; -- note std_ulogic not std_logic
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
53
RAM 16x1 (3)
begin
RAM_16x1s_1: ram16x1s generic map (INIT => X"0000")
port map
(O => DATA_OUT,
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DATA_IN,
WCLK => CLK,
WE => WE
);
end RAM_16X1_DISTRIBUTED_STRUCTURAL;
54
RAM 16x8 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity RAM_16X8_DISTRIBUTED is
port(
CLK : in STD_LOGIC;
WE : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
end RAM_16X8_DISTRIBUTED;
55
RAM 16x8 (2)
architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of
RAM_16X8_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro, only;
-- ignored during simulation
attribute INIT : string;
attribute INIT of RAM_16x1s_1: label is "0000";
component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
56
RAM 16x8 (3)
begin
GENERATE_MEMORY:
for I in 0 to 7 generate
RAM_16x1_S_1: ram16x1s
generic map (INIT => X"0000")
port map
(O => DATA_OUT(I),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DATA_IN(I),
WCLK => CLK,
WE => WE
);
end generate;
end RAM_16X8_DISTRIBUTED_STRUCTURAL;
57
ROM 16x1 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity ROM_16X1_DISTRIBUTED is
port(
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : out STD_LOGIC
);
end ROM_16X1_DISTRIBUTED;
58
ROM 16x1 (2)
architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of
ROM_16X1_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro, only;
-- ignored during simulation
attribute INIT : string;
attribute INIT of rom16x1s_1: label is "F0C1";
component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal Low : std_ulogic := '0';
59
ROM 16x1 (3)
begin
rom16x1s_1: ram16x1s
generic map (INIT => X"F0C1")
port map
(O=>DATA_OUT,
A0=>ADDR(0),
A1=>ADDR(1),
A2=>ADDR(2),
A3=>ADDR(3),
D=>Low,
WCLK=>Low,
WE=>Low
);
end ROM_16X1_DISTRIBUTED_STRUCTURAL;
60
Block RAM library components
Component
Data Cells
Parity Cells
Address Bus
Data Bus
Parity Bus
Depth
Width
Depth
Width
RAMB16_S1
16384
1
-
-
(13:0)
(0:0)
-
RAMB16_S2
8192
2
-
-
(12:0)
(1:0)
-
RAMB16_S4
4096
4
-
-
(11:0)
(3:0)
-
RAMB16_S9
2048
8
2048
1
(10:0)
(7:0)
(0:0)
RAMB16_S18
1024
16
1024
2
(9:0)
(15:0)
(1:0)
RAMB16_S36
512
32
512
4
(8:0)
(31:0)
(3:0)
61
Component declaration for BRAM (1)
-- Component Declaration for RAMB16_S1
-- Should be placed after architecture statement but before begin
component RAMB16_S1
-- synthesis translate_off
generic (
INIT : bit_vector := X"0";
INIT_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
…………………………………
INIT_3F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST");
-- synthesis translate_on
port (DO : out STD_LOGIC_VECTOR (0 downto 0)
ADDR : in STD_LOGIC_VECTOR (13 downto 0);
CLK : in STD_ULOGIC;
DI : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
SSR : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
62
Genaral template of BRAM instantiation (1)
-- Component Attribute Specification for RAMB16_{S1 | S2 | S4}
-- Should be placed after architecture declaration but before the begin
-- Put attributes, if necessary
-- Component Instantiation for RAMB16_{S1 | S2 | S4}
-- Should be placed in architecture after the begin keyword
RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1
-- synthesis translate_off
generic map (
INIT => bit_value,
INIT_00 => vector_value,
INIT_01 => vector_value,
……………………………..
INIT_3F => vector_value,
SRVAL=> bit_value,
WRITE_MODE => user_WRITE_MODE)
-- synopsys translate_on
port map (DO => user_DO,
ADDR => user_ADDR,
CLK => user_CLK,
DI => user_DI,
EN => user_EN,
SSR => user_SSR,
WE => user_WE);
63
Initializing Block RAMs 1024x16
INIT_00 : BIT_VECTOR :=
X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040";
INIT_01 : BIT_VECTOR :=
X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026";
INIT_02 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
DATA
……………………………………………………………………………………………………………………………………
ADDRESS
INIT_3F : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000")
INIT_00
014A
0C0F
0917
006A
ADDRESS
0F
0E
04
03
0068
02
0006
01
0040
00
INIT_01
ADDRESS
0000
1F
0000
1E
014A
14
0C0F
13
03AA
12
0917
11
0026
10
0000
F4
0000
F3
0000
F2
0000
F1
0000
F0
Addresses are
shown in red and
data corresponding
to the same
memory location is
shown in black
INIT_3F
ADDRESS
0000
FF
0000
FE
64
Component declaration for BRAM (2)
VHDL Instantiation Template for RAMB16_S9, S18 and S36
-- Component Declaration for RAMB16_{S9 | S18 | S36}
component RAMB16_{S9 | S18 | S36}
-- synthesis translate_off
generic (
INIT : bit_vector := X"0";
INIT_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST"; );
65
Component declaration for BRAM (2)
-- synthesis translate_on
port (DO : out STD_LOGIC_VECTOR (0 downto 0);
DOP : out STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (13 downto 0);
CLK : in STD_ULOGIC;
DI : in STD_LOGIC_VECTOR (0 downto 0);
DIP : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
SSR : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
66
Genaral template of BRAM instantiation (2)
-- Component Attribute Specification for RAMB16_{S9 | S18 | S36}
-- Component Instantiation for RAMB16_{S9 | S18 | S36}
-- Should be placed in architecture after the begin keyword
RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1
-- synthesis translate_off
generic map (
INIT => bit_value,
INIT_00 => vector_value,
. . . . . . . . . .
INIT_3F => vector_value,
INITP_00 => vector_value,
……………
INITP_07 => vector_value
SRVAL => bit_value,
WRITE_MODE => user_WRITE_MODE)
-- synopsys translate_on
port map (DO => user_DO,
DOP => user_DOP,
ADDR => user_ADDR,
CLK => user_CLK,
DI => user_DI,
DIP => user_DIP,
EN => user_EN,
SSR => user_SSR,
WE => user_WE);
67
Block RAM Waveforms – WRITE_FIRST
68
Block RAM Waveforms – READ_FIRST
69
Block RAM Waveforms – NO_CHANGE
70