Transcript Space Missions Comparison of the Proton SEU Performance of the Microblaze and the Leon2 Soft Core Processors as implemented on a Xilinx Virtex-II SRAM based.

Space Missions
Comparison of the Proton SEU
Performance of the Microblaze and
the Leon2 Soft Core Processors as
implemented on a Xilinx Virtex-II
SRAM based FPGA
David Hiemstra, Fayez Chayab,
and Kristopher Bates
Fayez Chayab
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Abstract
In this presentation, we report initial
results of Single-Event Upset (SEU) tests
and characterization of two industry
standard soft core processors, Xilinx’s
MicroBlaze and Gaisler Research’s
Leon2, as implemented on a Virtex-II
SRAM based FPGA.
Fayez Chayab
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Overview of Device Under Test
Virtex-II XC2V1000
• Consists of 1M system gates with a
core voltage of 1.5V.
• Fabricated on a 0.15μm / 0.12 μm
CMOS 8 layer metal process.
• Includes: dual ported block RAM,
dedicated multipliers, flexible logic
resources (configurable logic blocks
(CLBs) and flip-flops (FFs)), clock
management circuitry, extensive
routing resources, and programmable
I/O.
• 1280 CLBs, 10240 FFs, and 40
dedicated multipliers
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Virtex-II
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Overview of Device Under Test (cont’d)
The Virtex-II family of FPGAs are programmable SRAM-Based devices
Other than the conventional benefits of reprogrammable logic, such as:
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Faster prototyping
Hardware re-use
The allowance for on-orbit design changes
Solutions for space applications based on a System-on-Chip (SoC) implementation
that take advantage of industry standard soft-core Intellectual Properties (IPs), as
compared to the conventional single board computer approach, offer benefits such
as:
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Increased integration
System Level Re-configurability
Reduced mass, power, and volume
These benefits however come with additional upset susceptibility in the space
radiation environment.
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Like other SRAM based FPGAs the Virtex-II can experience upsets in their SRAM storing the
logic configuration resulting in single event functionality upsets and internal or external I/O
contentions.
More over, the presence of an embedded soft-core in the system, with its software, registers,
caches, and fixed logic, adds more levels of upset-able elements that could fail in more
spectacular modes than ever before.
Therefore, SEU testing and analyses, of two industry standard soft core processors,
Xilinx’s MicroBlaze and Gaisler Research’s Leon2, are undertaken to evaluate the
performance of these implementations in the space radiation environment.
Fayez Chayab
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Overview of Device Under Test (cont’d)
The MicroBlaze Architecture
Fayez Chayab
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Overview of Device Under Test (cont’d)
The Leon2 Architecture
RS232
Debug
Support Unit
5-Stage
Integer Unit
D-Cache
AHB
Controller
Debug
Serial Link
I-Cache
MMU
AMBA AHB
AHB/APB
Bridge
Memory
Controller
AMBA APB
UART
SDRAM
Fayez Chayab
RS422
I/O
Timers
DEBUG
Header
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PROM
Controller
Irq Ctrl
PROM
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Overview of Device Under Test (cont’d)
Leon2 / MicoBlaze Architectural Features Comparison
LEON2
MicroBlaze
Processor type
32-bit RISC
32-bit RISC
Byte ordering
Big Endian
Big Endian
Fully synthesizable VHDL model targetting
ASIC+FPGA
Parameterized netlist targetting Xilinx FPGAs
SPARC V8 ISA + support for 2 additional
coprocessors (FPU + custom)
MicroBlaze ISA + Fast Symplex Link (FSL) to
Custom hardware
Instruction Format
3
2
Addressing Modes
immediate, displacement, index
Immediate, displacement
Integer Unit
Single issue, 5-stage pipeline, 5 multipliers
(HW/SW), radix-2 division, MAC
Single issue, 3-stage pipeline, multiplication,
division
Register file
2-32 register windows, 8 registers/window
2-32 register windows, 8 registers/window
Cache sub-system
Harvard Architecture
1-64 KB, direct mapped or 2-4 way set associative
data + instruction, replacement (LRU, LRR,
pseudo-random) cache line locking
Harvard Architecture
2-64 KB direct mapped data + instruction
cache line locking
MMU
Shared or TLB fully associated, 2-32 entries 4KB,
256KB, 16MB page size
No support
AMBA AHB, APB pipelined operation, burst
transfers, support for multiple masters
Local Memory Bus (LMB), IBM CoreConnect
OPB (multi-master / multi-slave), Fast Simplex
Link
Memory Controller
PROM, SRAM, SDRAM, memory-mapped I/O
SRAM, SDRAM, DDR, memory-mapped I/O
Debug Support
Debug Support Unit Serial Communication link
access to system bus
MicroBlaze Processor Debug Module (MDM)
Model
ISA
System Interface
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Proton Irradiation
Protons for SEE Characterization versus Heavy Ions
• Proton irradiation can be performed in air.
• Not required to delid components.
• Can be extremely difficult for COTS components.
• Irradiation facility cost in general is significantly lower.
• Upset due to protons can be a major contributor compared to heavy ions.
• For low earth orbit irradiation with 200 MeV protons to 1010 p/cm2 covers a
majority of SEE due to heavy ions.
• Empirical Figure Of Merit (FOM) allows calculation of the heavy ion SEU
rate from proton test data.
• Total dose proton data can be obtained at the same time.
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Proton Irradiation (cont’d)
Experimental test setups
TRIUMF Proton Irradiation
Facility Specifications
Beam Line 1B
Beam Line 2C
180  520
65  120
120  180
by degrader
20  65
by degrader
105  4x107
105  108
4  225
1  49
Energy (MeV)
Intensity
(protons/cm2/s)
Field Size
Square (cm2)
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Test: Methodology, Setup, and Procedure
Utilized Hardware:
•
Target Board:
Memec Design Virtex-II V2MB1000 Development Board
with P160 Comm2
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Device Family:
Device:
Package:
Speed Grade:
Processor:
System clock:
Debug:
Data Cache:
Instr Cache:
On Chip Memory:
Off Chip Memory:
Other Interfaces:
Fayez Chayab
Virtex2
XC2V1000
FG456
-4
Microblaze/Leon2
24 MHz
XMD/DSU
8 KB
8 KB
32 KB (Boot Mem)
SRAM_256Kx32 (Program Mem)
RS232 Uart
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Test: Methodology, Setup, and Procedure (cont’d)
In-Beam System Setup:
• A desktop PC was utilized for FPGA
configuration, and target processor
debugging, while the Serial Port was
used for code image downloads and
error and data logging
DC
Power
Supply
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Reset
DCM
IRRADIATION ROOM
CONTROL ROOM
POWER BAR
LECROY
OSCILLOSCOPE
RS232
INT
CNTRL
SRAM
CNTRL
JTAG Cable
Fayez Chayab
MicroBlaze/Leon2
Embedded 32Bit Soft Core
BOOT
BRAM
Serial Cable
• Finally, the power to the DUT could
be recycled from the control room
Extension Cord
• For latchup detection a digital scope
coupled with a current probe were
utilized
Processor
Bus
JTAG
CNTRL
Current
Probe
Current Monitor
• The desktop PC was located in the
irradiation room and an extension kit
was used to control and monitor it
from the adjacent control room
DUT
XC2V1000-4FG456C
Host PC
configuration
&
Data Logging
Program
MEM
Monitoring
Work
Station
PC Extender
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Test: Methodology, Setup, and Procedure (cont’d)
Test Codes and Variants:
Test Name
Failure Modes
# of Variants
Iterative (1000each)
Integer Multiplication,
Division, Addition, and
Subtraction
Errors in calculated
results
2 variants
Cache On /
Cache OFF
Memory Test
Testing Memory Control
Logic through Read, Write,
and Pattern Fills
Bit flips or errors in
read-back memory
patterns
2 variants
Cache On /
Cache OFF
Timer
&
Interrupt Test
Setup a predefined timer
count to generate
interrupts
Timer or Interrupt
errors
2 variants
Cache On /
Cache OFF
ALU Test
Full Test
Fayez Chayab
Functionality
A sequential Execution of
all the above Tests
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All the above
2 variants
Cache On /
Cache OFF
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Test: Results
Fayez Chayab
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Test: Results (cont’d)
Evaluated Designs’ SEU Upset Rates:
The proton SEU cross-sections and the upset rates, using the FOM technique on
the Space Shuttle, assuming 2.5” Al shielding, in a space station orbit (57, 555.6 km,
circular), for the above mentioned reference designs are given below:
Leon2:
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ALU_TEST_CACHE_ON =
ALU_TEST_CACHE_OFF =
MEM_TEST_CACHE_ON =
MEM_TEST_CACHE_OFF =
TIMER_TEST_CACHE_ON =
TIMER_TEST_CACHE_OFF =
FULL_TEST_CACHE_ON =
FULL_TEST_CACHE_OFF =
4.24 x10-9 cm2/design
3.97 x10-9 cm2/design
3.79 x10-9 cm2/design
2.29 x10-9 cm2/design
8.00 x10-9 cm2/design
4.02 x10-9 cm2/design
4.02 x10-9 cm2/design
4.46 x10-9 cm2/design
0.00424/day
0.00397/day
0.00379/day
0.00229/day
0.00800/day
0.00402/day
0.00402/day
0.00446/day
2.04 x10-9 cm2/design
1.40 x10-9 cm2/design
3.18 x10-9 cm2/design
2.46 x10-9 cm2/design
1.99 x10-9 cm2/design
2.14 x10-9 cm2/design
1.65 x10-9 cm2/design
2.25 x10-9 cm2/design
0.00204/day
0.00140/day
0.00318/day
0.00246/day
0.00199/day
0.00214/day
0.00165/day
0.00225/day
MicroBlaze:
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ALU_TEST_CACHE_ON =
ALU_TEST_CACHE_OFF =
MEM_TEST_CACHE_ON =
MEM_TEST_CACHE_OFF =
TIMER_TEST_CACHE_ON =
TIMER_TEST_CACHE_OFF =
FULL_TEST_CACHE_ON =
FULL_TEST_CACHE_OFF =
Fayez Chayab
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Test: Results (cont’d)
SEU Comparison Charts:
9
ALU_Te s t_Cache _ON
8
ALU_Te s t_Cache _OFF
7
M EM _Te s t_Cache _ON
6
5
M EM _Te s t_Cache _OFF
4
Tim e r _Te s t_Cache _ON
3
Tim e r _Te s t_Cache _OFF
2
Full_Te s t_Cache _ON
1
0
Full_Te s t_Cache _OFF
LEON2 Cross-Sections
3.5
ALU_Te s t_Cache _ON
3
ALU_Te s t_Cache _OFF
2.5
M EM _Te s t_Cache _ON
2
1.5
1
0.5
0
M EM _Te s t_Cache _OFF
Tim e r _Te s t_Cache _ON
Tim e r _Te s t_Cache _OFF
Full_Te s t_Cache _ON
Full_Te s t_Cache _OFF
MicroBlaze Cross-Sections
Fayez Chayab
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Conclusions
• Embedded soft-core processors provide considerable advantages for SoC
designs targeted at space applications as previously described.
• Based on the results of the authors’ initial attempt at characterizing this
relatively new technology of soft-core embedded processors, more work
needs to be performed to fully characterize this technology for the following
reasons:
•
•
As analysis of the gathered data was conducted, it was difficult to evaluate
some of the modes of recorded failures as results of FPGA Configuration
memory upsets or embedded core / fabric upsets.
Future test designs utilizing Fabric Mitigation Techniques such as
Configuration memory scrubbing and Triple Mode Redundancy (TMR) will
help in shedding more light on to the previously mentioned error modes.
Fayez Chayab
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