Transcript Group 6 You’ve Got SARS!! Brent Anderson Lauren Cutsinger Martin Gilpatric Michael Oberg Matthew Taylor Capstone Spring 2006

Group 6
You’ve Got SARS!!
Brent Anderson
Lauren Cutsinger
Martin Gilpatric
Michael Oberg
Matthew Taylor
Capstone Spring 2006
Presentation Outline

Milestones

Logistics

Enhancements to Core Design

Bus Interconnectivity

Program Flow

Client GUI

Motor Control

Demonstrations
Project Overview

Design an infrared tracking system that will
control a motorized camera platform.

Track infrared image of person.

Display IR image.

Determine temperature of person for possible
disease detection.
System Overview
PWM
SPI
4431
Major Components
IR Camera
 PIC Processors
 Camera Mount
 Motors
 PCB
 Output (PC)

4550
USB 2.0
Milestones
Milestone 1
–
–
–
–
Complete Prototype
Basic Motor Control
Talk to IR Camera over SPI
Basic Tracking Abilities
Milestone 2
–
–
–
–
–
PCB with Surface Mount Components
Advanced Tracking
Fine Tuned Motor Control
Camera Mounted with Optics
Basic PC Interface
Expo
–
–
Full Camera Integration
Complete PC Interface
Tasks
Team Member
Brent
Main Tasks
•
•
Lauren
•
•
Martin
•
•
Michael
•
•
Matthew
•
•
Core Chip Programming
Overall Product Design and Prototyping
PCB Layout
Mechanical Assembly
Targeting Software
UART Interfacing
Image Post-Processing
PC Client Interface
PCB Layout
Motor Interfacing
Costs (Overall - Vendor)
Vendor
Amount
Lynxmotion
$43.86
Sparkfun
$21.51
DigiKey
$17.09
Dexter
$850.00
Total
$932.46
UROP Funds
$800.00
Costs (Specific)
Part
Cost
Thermopile Array
$850.00
Misc. Connectors
$13.82
Crystal Oscillator
$5.01
Misc. Parts
$11.28
Camera Mount and Servos
$35.93
Total
$916.04
Schematics

Voltage Regulator

Processor Board

Breakout Board

Motor Control Board
Res1
?
R
Res1
uF
100
?
R
2
C
Reg
Volt
uF
100
uF
10
2
C
1
C
D
N
G
OUTPUT
5V
Vout
Vin
VR?
PWR2.5
1
LED
3
5
D
2
1
J
SW-PB
1
S
Schematics – Voltage Regulator
Cap
Cap
VCC
VCC
6
C
5
C
PIC18F4550-E/PT
PIC18F4550-E/PT
D
7
D
D
V
D
VSS
V
VSS
9
2
D
7
D
D
V
D
VSS
V
VSS
5
3
8
RC1/T1OSI/CCP2(1)/-UOE
8
1
2
6
5
3
8
2
MCLR/VPP/RE3
RC1/T1OSI/CCP2(1)/-UOE
MCLR/VPP/RE3
8
1
6
9
2
RC2/CCP1/P1A
NC/ICPORTS(2)
RC2/CCP1/P1A
NC/ICPORTS(2)
6
3
4
3
6
3
4
3
NC/-ICRST(2)/ICVPP(2)
NC/-ICRST(2)/ICVPP(2)
3
3
3
3
NC/ICDT(2)/ICPGD(2)
NC/ICDT(2)/ICPGD(2)
3
1
3
1
RE2/AN7/OESPP
NC/ICCK(2)/ICPGC(2)
RE2/AN7/OESPP
NC/ICCK(2)/ICPGC(2)
7
2
2
1
7
2
2
1
RE1/AN6/CK2SPP
RE1/AN6/CK2SPP
6
2
6
2
OSC2/CLKO/RA6
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
2
4
RA3/AN3/VREF+
RD5/SPP5/P1B
RA3/AN3/VREF+
2
3
2
2
RA2/AN2/VREF-/CVREF
RD4/SPP4
RA2/AN2/VREF-/CVREF
2
1
2
RE0/AN5/CK1SPP
OSC1/CLKI
5
2
0
1
RD7/SPP7/P1D
5
4
RD6/SPP6/P1C
4
3
RD5/SPP5/P1B
3
2
RD4/SPP4
2
1
2
3
2
5
RD6/SPP6/P1C
RA4/T0CKI/C1OUT/RCV
3
2
C
3
RD7/SPP7/P1D
RA5/AN4/SS/HLVDIN/C2OUT
4
2
4
3
5
2
OSC2/CLKO/RA6
1
3
C
RE0/AN5/CK1SPP
OSC1/CLKI
0
3
RD3/SPP3
RA1/AN1
RD3/SPP3
RA1/AN1
1
4
0
2
1
4
0
2
1
C
2
C
RD2/SPP2
RA0/AN0
RD2/SPP2
RA0/AN0
0
4
9
1
0
4
9
1
RD1/SPP1
RD1/SPP1
9
3
9
3
RD0/SPP0
RB7/KBI3/PGD
RD0/SPP0
RB7/KBI3/PGD
8
3
7
1
8
3
7
1
RB6/KBI2/PGC
RB6/KBI2/PGC
6
1
6
1
RC7/RX/DT/SDO
RB5/KBI1/PGM
RC7/RX/DT/SDO
RB5/KBI1/PGM
1
5
1
1
5
1
RC6/TX/CK
RB4/AN11/KBI0/CSSPP
RC6/TX/CK
RB4/AN11/KBI0/CSSPP
4
4
4
1
4
4
4
1
RC5/D+/VP
RB3/AN9/CCP2(1)/VPO
RC5/D+/VP
RB3/AN9/CCP2(1)/VPO
3
4
1
1
3
4
1
1
RC4/D-/VM
RB2/AN8/INT2/VMO
RC4/D-/VM
RB2/AN8/INT2/VMO
2
4
0
1
2
4
0
1
VUSB
RB1/AN10/INT1/SCK/SCL
VUSB
RB1/AN10/INT1/SCK/SCL
7
3
9
7
3
9
RC0/T1OSO/T13CKI
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RB0/AN12/INT0/FLT0/SDI/SDA
2
3
8
2
3
8
2
U
1
U
8X2
Header
4
1
3
1
6
1
5
1
2
1
1
1
0
1
9
8
7
6
5
VCC
4
3
2
1
1
P
Schematics - Processor
6
Header
6
Header
3
P
2
P
1
2
3
4
5
6
1
2
3
4
5
6
VCC
VCC
MAX233
C2+
(V-)CS-
2
1
1
-
V
C1-
1
3
+
V
1
4
C2+
D
G
D
Vdc
7
N
(v+)C1+
8
?
C
N
G
9
1
0
1
Pol1
Cap
9
Header
9
Header
5
1
6
1
VCC
9
C2-
T1Out
2
6
1
5
8
3
7
-
V
R1In
4
7
1
4
6
5
5
T2Out
R1Out
6
8
1
3
4
7
3
R2In
T1In
8
9
1
2
2
9
1
R2Out
T2In
0
2
1
4
P
5
P
*
8X2
Header
4
1
6
3
1
1
5
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
1
P
VCC
Schematics – Breakout Board
Enhancements to Core Design

Smaller design – all surface mount parts

Faster communications with USB 2.0

Off-board Programming header

New motor control PIC processor with better
PWM precision
Benefits of smaller design



Daughter board connection to camera
Small casing and camera mount
Minimal connections to camera
–
–

Mini USB
Power
Looks cool!
Benefits of Breakout Board

Smaller main PCB

Great debugging tool

Off-board Programming header

Adds serial connector with very little space
Benefits of USB 2.0

Faster frame rate (up to 30 fps, limited by SPI and camera)

Goes around problem of multiuse pin (RX and SPI)

Allows us to bring RS232 out to breakout board

Very small connector to save even more space

If power constraints work, use USB to power entire board
Benefits of the 4331 Motor Control PIC

Better motor control

RS232 not multiplexed with SPI, so more
debug control (manual control)

Don't have to slow down processor, allowing
more speed for processing frames

Better precision and more fine tuned control
Camera Communications
Component Interconnect
Two bus types:
1)SPI
-Connects the camera and
the two processors
-3 lines: MISO, MOSI, SCK.
2)RS 232
-Using single line: TX
-Only transmitting from one
processor to the PC
SPI


3 Line Serial Standard (with enable lines).
–
MISO: Master in, Slave out.
–
MOSI: Master out, Slave in.
–
SCK: SPI clock.
–
Individual enable lines for each slave.
SPI communication method:
–
Enable slave: Set appropriate enable line high.
–
Master: Write to SPI Register (SPI module will load SPI shift register from this buffer)
–
SPI module will clock data out and receive data sent by the slave.

Data is clocked into and out of the slave via the SPI clock.
SPI
SPI “Spying”


Reasoning:
–
Require same image data on both processors.
–
Using the SPI bus twice would waste time.
Method:
–
Second PIC is connected to the bus as if it were a master: SDI tied to MISO, SDO tied to MOSI.
–
Second PIC enables SPI as a slave: does not generate SCK, uses SS as SPI receive enable.
–
Enable is same line as the camera’s data SPI output enable
–
When Master requests data from camera it will clock data from the camera which will be output to
the MOSI which is tied to the SDI of both processors. The master generating the clock will receive
the data as it would without the second processor. The Second PIC will have data clocked in as if it
were receiving it from a normal SPI Master.
RS 232

Normally a 2 line serial connection.

Using only TX, the transmit line.

Options:

115200 baudrate

No parity bit

8 bit data

1 stop bit

Currently using Tera Term to interpret received data.

Potentially being replaced by USB 2.0 for greater speed.
Pin Outs
PIC 1
PIC 2
Pin #
Connection
Pin #
Connection
2
Fun Little LED
2
ARRAY_RESET
8
~ARRAY/LM20
15
PWM
9
~TEST/RUN
16
PWM
15
ADC select
33
SPI Data In
16
DAC select
34
SPI Clock
17
MUX select
23
USB D-
24
USB D+
25
TX
26
SPI Data Out
33
SPI Data In
34
SPI Clock
35
ARRAY_CLK
36
ARRAY_RESET
Program Flow

PIC 1: Acting as Master of the SPI bus/ Relaying Image to PC
–
Initialisation:

–
Interact with camera:




–

Set appropriate control registers for both RS 232 and SPI
Reset Thermopile array.
Begin loop to access all values on the thermopile array.
through SPI, set MUX to appropriate output and read output from ADC.
Repeat loop until array has been completely relayed, the issue reset to thermopile and begin again.
Relay information to PC through RS 232.
PIC 2: “Spy” on SPI bus to acquire image data/ Process image for tracking
–
Initialisation:

–
Set appropriate control registers for SPI and PWM.
Spy on SPI bus:







Wait for reset to be sent to thermopile. Indicates beginning of picture.
Begin loop to generate running averages of both columns and rows.
Read in value from SPI and add it to the appropriate portions of column averages and row averages.
Leave loop when all 1024 values have been appropriately processed.
Process image via column and row averages to generate targeting information.
Change direction of camera as necessary.
Wait for reset signal, then begin loop again.
Client Software Outline

Architecture

Block Diagrams

Current Implementation
Client Architecture


Ubuntu Linux
–
Easy to install, configure, secure
–
Up to date packages
Client written in C
–

Good choice for interaction with Serial/USB, and GTK+
GTK+ 2.8.6 Graphical User Interface Library
–
Cross-Platform (also supports Windows)
–
~ 2800 functions, from high level convenience functions to low
level routines for fine tuned control
Client Block Diagram
Client Block Diagram
Client Screenshot
Motor Control and Implementation
Parts List:

PIC18F4431 (Specialized For Motor Control)
–
–
–



14 Bits of accuracy on Duty and Period Registers
Large Prescalers and Postscalers
Comparable to PIC18F4550
2 Hitec-422 Servos
HC_HCPL-2730 Optocouplers
MAX4426 1.5A MOSFET Drivers
3
3
SPGND
8
2
SP+5
B
1
5
4
Servo2
A
7
2
D
D
V
C
N
3
Header
SP+5
6
1
?
U
3
SPGND
2
SP+5
HCPL-2730
1
D
+Vf2
N
G
4
5
-Vf2
Vo2
3
6
-Vf1
Vo1
Servo1
Optocouple
r
Header
C
N
D
N
G
3
SPGND
Servo Power
MAX4427EJA
MOSFET
Driver
SPGND
2
Header
2
7
1
SPGND
+Vf1
Vcc
2
1
8
SP+5
SP+5
*
Power
Motor
PWM2
PWM1
VCC
Servo Schematic
Main Power
Servo Headers
HiTec HS-422 Servo Constraints
Controlled With PWM signalling


20ms Signal Refresh (50Hz)
.9ms to 2.1ms active high position definition range
–

With PIC18F4550 achieved 5° of precision
–

Duty Cycle from 4.5% 10%
Maximum Oscillation freq 500Khz
PIC18F4431 can achieve servo constraints at 40MHz
–
High Degree of accuracy over 1°
PWM Control Signal
0° 4.5% Duty Cycle @50Hz
180° 10% Duty Cycle @50Hz
Demonstrations, and Questions?