Transcript Introduction to MOS Transistors Section 6.1-6.4 Selected Figures in Chapter 15 Outline • • • • Review of NMOS Introduction of PMOS Application of CMOS in Digital Circuits Small Signal Model.

Introduction to MOS
Transistors
Section 6.1-6.4
Selected Figures in Chapter 15
Outline
•
•
•
•
Review of NMOS
Introduction of PMOS
Application of CMOS in Digital Circuits
Small Signal Model
Introductory Device Physics
A Crude Metal Oxide
Semiconductor (MOS) Device
P-Type Silicon is
slightly conductive.
The gate
draws no current!
Positive charge attract
negative charges
to the interface between
insulator and silicon.
V2 causes movement
of negative charges,
thus current.
V1 can control the
A conductive path is created resistivity of the channel.
If the density of electrons is
sufficiently high.
Q=CV.
Typical Dimensions of MOSFETs
tox is made really thin
to increase C, therefore,
create a strong control of Q by V.
These diode must
be reversed biased.
A Closer Look at the Channel
Formulation
Need to tie substrate to GND
to avoid current through PN
diode.
(OFF)
(ON)
VTH=300mV to 500 mV
Free electrons appear at VG=VTH.
Positive charges repel the holes
creating a depletion region, a region free of holes.
VG-VD is sufficiently large
to produce a channel
No channel
VG-VD is NOT sufficiently large
to produce a channel
Electrons
are swept
by E to drain.
Drain can no longer affect the drain current!
Regions
(No Dependence on VDS)
No channel
Assumption:
Graphical Illustration
Determination of Region
TYPO: ON
Determine Region of
Operation (6.19)
Tricky!
Assume that VTHN=0.4 V and VTHP=-0.4 V
PMOS in Cut-Off Mode
----------
P+
P+
N+
N
P
Substrate= 0V
PMOS: Formation of Channel
----------
P+
++++++++++
P+
N+
N
P
Substrate= 0V
Induced holes
PMOS in Triode Region
------ --
P+
+++++++++
P+
N+
N
P
Substrate= 0V
Induced holes
PMOS in Saturation Region
----- --
P+
++++++++
P+
N+
N
P
Substrate= 0V
Induced holes
PMOS Transistor
Determine Region of
Operation (6.40)
Assume that VTHN=0.4 V and VTHP=-0.4 V
NMOS Inverter
VGS=VCC, Switch is ON.
VGS=0 V, Switch is OFF.
PMOS Inverter
VSG=VCC, switch is off.
VSG=0, switch is on.
Mysterious 2-Input Logic Gate
Exercise In Class
NAND Gate
Small Signal Model
Limited VDS Dependence In
Saturation
As VDS increase,
effective L decreases,
therefore, ID increases.
Pronounced Channel Length
Modulation in small L
Similarity to Early Effect
A larger reverse bias voltage leads to a
larger BC depletion region.
The effective base width (WB) is reduced.
The slope of the electron profile increases.
IC increases as VCE is increased.
Output Resistance
ro 
1
I D
Transconductance
• As a voltage-controlled current source, a MOS
transistor can be characterized by its
transconductance:
• It is important to know that
Compare NMOS Equation to
PMOS Equation
(Cut-off)
(triode)
Valid for NMOS
(saturation)
(saturation)
(triode)
(Cut-off)
Valid for PMOS
Small Signal Model for Both
BJT AND CMOS
Exercise Slides
Determine Region of
Operation (6.19)
Tricky!
Assume that VTHN=0.4 V and VTHP=-0.4 V
Determine Region of
Operation (6.40)
Assume that VTHN=0.4 V and VTHP=-0.4 V
NMOS Inverter
VGS=VCC, Switch is ON.
VGS=0 V, Switch is OFF.
PMOS Inverter
VSG=VCC, switch is off.
VSG=0, switch is on.
Mysterious 2-Input Logic Gate
Exercise In Class
Optional Slides
VA=5 V
VA=0 V