Transcript Sequential Logic Optimization  State Minimization Algorithms for State Minimization  State, Input, and Output Encodings Minimize the Next State and Output logic CS 150

Sequential Logic Optimization
 State Minimization
Algorithms for State Minimization
 State, Input, and Output Encodings
Minimize the Next State and Output logic
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 1
Midterm II
 Wednesday, 9 November, in 125 Cory, 1-2:30 PM
TA led review session on Monday--what newsgroup for place
and time
No regular class lecture--Prof. Katz goes to Singapore!
 Same ground rules as before:
Double sided crib sheet, closed book and notes
Bring pencil and eraser!
All work to be done on exam sheets -- do NOT bring
bluebooks
If you split the exam into separate sheets, be sure to bring a
stapler to put it back together again!
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 2
Midterm II
 Topics to be covered
Lectures #10 through #16: Verilog synthesis, Memory
systems, Project concept, Datapath design (including tristates vs. mux), Controller design and implementation
(classical, time state, jump counter, microprogram-horizontal, vertical) plus Project checkpoints #1, #2, #3
Understand the design and implementation process:
Specification/data sheet/timing diagrams define behavior
Datapath/register transfer/control operations
State diagrams or verilog programs to implement desired
behavior
Operational timing to make register transfer work!
Section 4.4, 7.3, 9.1, 9.2, 9.5, 10.1-10.4 + supplementary
readings on the course website
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 3
Optimization in Context
 Understand the word specification
 Draw a picture
 Derive a state diagram and Symbolic State Table
 Determine an implementation approach (e.g., gate logic, ROM,
FPGA, etc.)
 Perform STATE MINIMIZATION
 Perform STATE ASSIGNMENT
 Map Symbolic State Table to Encoded State Tables for
implementation (INPUT and OUTPUT encodings)
 You can specify a specific state assignment in your Verilog code
through parameter settings
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 4
Finite State Machine Optimization
 State Minimization
Fewer states require fewer state bits
Fewer bits require fewer logic equations
 Encodings: State, Inputs, Outputs
State encoding with fewer bits has fewer equations to implement
However, each may be more complex
State encoding with more bits (e.g., one-hot) has simpler
equations
Complexity directly related to complexity of state diagram
Input/output encoding may or may not be under designer control
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 5
Algorithmic Approach to State Minimization
 Goal – identify and combine states that have equivalent behavior
 Equivalent States:
 Same output
 For all input combinations, states transition to same or equivalent
states
 Algorithm Sketch
 1. Place all states in one set
 2. Initially partition set based on output behavior
 3. Successively partition resulting subsets based on next state
transitions
 4. Repeat (3) until no further partitioning is required
states left in the same set are equivalent
 Polynomial time procedure
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 6
State Minimization Example
 Sequence Detector for 010 or 110
0/0
0/0
S3
0/0
S1
1/0
S0
0/0
S4
S5
0/1
Next State
Present State X=0
X=1
Output
X=0
X=1
Reset
0
1
00
01
10
11
S0
S1
S2
S3
S4
S5
S6
0
0
0
0
1
0
1
S1
S3
S5
S0
S0
S0
S0
S2
S4
S6
S0
S0
S0
S0
1/0
1/0
1/0
Input
Sequence
0/0
S2
1/0
1/0
S6
0/1
1/0
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 7
0
0
0
0
0
0
0
Method of Successive Partitions
Input
Sequence
Next State
Present State X=0
X=1
Output
X=0
X=1
Reset
0
1
00
01
10
11
S0
S1
S2
S3
S4
S5
S6
0
0
0
0
1
0
1
S1
S3
S5
S0
S0
S0
S0
( S0 S1 S2 S3 S4 S5 S6 )
( S0 S1 S2 S3 S5 ) ( S4 S6 )
( S0 S1 S2 ) ( S3 S5 ) ( S4 S6 )
S2
S4
S6
S0
S0
S0
S0
0
0
0
0
0
0
0
S1 is equivalent to S2
S3 is equivalent to S5
S4 is equivalent to S6
( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 )
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 8
Minimized FSM
 State minimized sequence detector for 010 or 110
Input
Sequence
Next State
Present State X=0
X=1
Output
X=0
X=1
Reset
0+1
X0
X1
S0
S1'
S3'
S4'
0
0
0
1
S1'
S3'
S0
S0
S1'
S4'
S0
S0
0
0
0
0
S0
7 States reduced to 4 States
3 bit encoding replaced by 2 bit encoding
X/0
0/0
S1’
1/0
S4’
S3’
X/0
0/1
1/0
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 9
Another Example
 4-Bit Sequence Detector: output 1 after each 4-bit input
sequence consisting of the binary strings 0110 or 1010
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 10
State Transition Table
 Group states with same next state and same outputs
S’10
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 11
Iterate the Row Matching Algorithm
S’7
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 12
Iterate One Last Time
S’3
S’4
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 13
Final Reduced State Machine
15 states (min 4 FFs) reduced to 7 states (min 3 FFs)
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 14
More Complex State Minimization
 Multiple input example
inputs here
00
10
00
S0
[1]
01
10
S2
[1]
01
11
10
01
S4
[1]
S3
[0]
11
10
10
00
present
state
S0
S1
S2
S3
S4
S5
11
00 01
01
11
00
10
S1
[0]
11
01
S5
[0]
00
11
00
S0
S0
S1
S1
S0
S1
next state
01 10 11
S1 S2 S3
S3 S1 S4
S3 S2 S4
S0 S4 S5
S1 S2 S5
S4 S0 S5
symbolic state
transition table
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 15
output
1
0
1
0
1
0
Minimized FSM
 Implication Chart Method
Cross out incompatible states based on outputs
Then cross out more cells if indexed chart entries are
already crossed out
S1
S2
S0-S1
S1-S3
S2-S2
S3-S4
S3
S4
S0-S0
S1-S1
S2-S2
S3-S5
S5
S0
S0-S1
S3-S0
S1-S4
S4-S5
S0-S1
S3-S4
S1-S0
S4-S5
S1
S1-S0
S3-S1
S2-S2
S4-S5
S2
S1-S1
S0-S4
S4-S0
S5-S5
S3
S4
present
state
S0
S1
S2
S3
S4
S5
next state
01 10 11
S1 S2 S3
S3 S1 S4
S3 S2 S4
S0 S4 S5
S1 S2 S5
S4 S0 S5
00
S0
S0
S1
S1
S0
S1
present
state
S0'
S1
S2
S3'
next state
00 01 10 11
S0' S1 S2 S3'
S0' S3' S1 S3'
S1 S3' S2 S0'
S1 S0' S0' S3'
minimized state table
(S0==S4) (S3==S5)
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 16
output
1
0
1
0
1
0
output
1
0
1
0
Minimizing Incompletely Specified FSMs
 Equivalence of states is transitive when machine is fully specified
 But its not transitive when don't cares are present
e.g.,
state output
S0
S1
S2
–0
1–
–1
S1 is compatible with both S0 and S2
but S0 and S2 are incompatible
 No polynomial time algorithm exists for determining best grouping of
states into equivalent sets that will yield the smallest number of final
states
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 17
Minimizing States May Not Yield Best Circuit
 Example: edge detector - outputs 1 when last two
input changes from 0 to 1
X’
00
[0]
X’
01
[1]
X
X’
11
[0]
X
X
0
0
0
1
1
1
–
Q1
0
0
1
0
0
1
1
Q0
0
1
1
0
1
1
0
Q1 +
0
0
0
0
1
1
0
X
Q1+ = X (Q1 xor Q0)
Q0+ = X Q1’ Q0’
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 18
Q0+
0
0
0
1
1
1
0
Another Implementation of Edge Detector
 "Ad hoc" solution - not minimal but cheap and fast
X’
X’
10
[0]
X’
00
[0]
X
X
01
[1]
X’
11
[0]
X
X
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 19
State Assignment
 Choose bit vectors to assign to each “symbolic” state
With n state bits for m states there are 2n! / (2n – m)!
[log n <= m <= 2n]
2n codes possible for 1st state, 2n–1 for 2nd, 2n–2 for 3rd, …
Huge number even for small values of n and m
Intractable for state machines of any size
Heuristics are necessary for practical solutions
Optimize some metric for the combinational logic
Size (amount of logic and number of FFs)
Speed (depth of logic and fanout)
Dependencies (decomposition)
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 20
State Assignment Strategies
 Possible Strategies
Sequential – just number states as they appear in the state table
Random – pick random codes
One-hot – use as many state bits as there are states (bit=1 –>
state)
Output – use outputs to help encode states
Heuristic – rules of thumb that seem to work in most cases
 No guarantee of optimality – another intractable problem
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 21
One-hot State Assignment
 Simple
 Easy to encode, debug
 Small Logic Functions
 Each state function requires only predecessor state bits as input
 Good for Programmable Devices
 Lots of flip-flops readily available
 Simple functions with small support (signals its dependent upon)
 Impractical for Large Machines
 Too many states require too many flip-flops
 Decompose FSMs into smaller pieces that can be one-hot encoded
 Many Slight Variations to One-hot
 One-hot + all-0
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 22
State Maps and Counting Bit Changes
Bit Change Heuristic
0
S0
1
S1
S2
S3
S4
S0 -> S1: 2
S0 -> S2: 3
S1 -> S3: 3
S2 -> S3: 2
S3 -> S4: 1
S4 -> S1: 2
Total:
13
1
1
1
1
1
2
7
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 23
Adjacency Heuristics for State Assignment
 Adjacent codes to states that share a common next state
Group 1's in next state map
a
I
i
i
Q
a
b
Q+
c
c
O
j
k
i/j
c=i*a + i*b
b
i/k
c
 Adjacent codes to states that share a common ancestor state
Group 1's in next state map

I
i
Adjacentk
Q+
Q
O
a
b
j
a
cto states
l
codes
i/j
b=i *a
c=k*a
a
k/l
b
c
that have a common output behavior
Group 1's in output map
I
i
i
Q
a
c
Q+
b
d
O
j
j
j=i *a+ i *c
b=i*a
d=i*c
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 24
a
c
i/j
i/j
b
d
Heuristics for State Assignment
Successor/Predecessor Heuristics
 High Priority: S’3 and S’4
share common successor
state (S0)
 Medium Priority: S’3 and S’4
share common predecessor
state (S’1)
 Low Priority:
 0/0: S0, S’1, S’3
 1/0: S0, S’1, S’3, S’4
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 25
Heuristics for State Assignment
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 26
Another Example
High Priority:
S’3, S’4
S’7, S’10
Medium Priority:
S 1, S 2
2 x S’3, S’4
S’7, S’10
Low Priority:
0/0: S0, S1, S2, S’3, S’4, S’7
1/0: S0, S1, S2, S’3, S’4, S’7, S10
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 27
Example Continued
 Choose assignment for S0 = 000
 Place the high priority adjacency
state pairs into the State Map
 Repeat for the medium adjacency
pairs
 Repeat for any left over states, using
the low priority scheme
Two alternative
assignments
at the left
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 28
Why Do These Heuristics Work?
 Attempt to maximize adjacent groupings of 1’s in the next state
and output functions
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 29
General Approach to Heuristic State
Assignment
 All current methods are variants of this
 1) Determine which states “attract” each other (weighted pairs)
 2) Generate constraints on codes (which should be in same cube)
 3) Place codes on Boolean cube so as to maximize constraints satisfied
(weighted sum)
 Different weights make sense depending on whether we are
optimizing for two-level or multi-level forms
 Can't consider all possible embeddings of state clusters in Boolean
cube
 Heuristics for ordering embedding
 To prune search for best embedding
 Expand cube (more state bits) to satisfy more constraints
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 30
Output-Based Encoding
 Reuse outputs as state bits - use outputs to help
distinguish states
Why create new functions for state bits when output can
serve as well
Fits in nicely with synchronous Mealy implementations
Inputs
C
TL
0
–
–
0
1
1
–
–
–
–
1
0
0
–
–
1
–
–
–
–
Present State
TS
–
–
–
0
1
–
–
–
0
1
HG
HG
HG
HY
HY
FG
FG
FG
FY
FY
HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0
HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’
FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’
HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0
Next State
HG
HG
HY
HY
FG
FG
FY
FY
FY
HG
Outputs
ST H
0
00
0
00
1
00
0
01
1
01
0
10
1
10
1
10
0
10
1
10
F
10
10
10
10
10
00
00
00
01
01
Output patterns are unique to states, we do not
need ANY state bits – implement 5 functions
(one for each output) instead of 7 (outputs plus
2 state bits)
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 31
Current State Assignment Approaches
 For tight encodings using close to the minimum number of state
bits
 Best of 10 random seems to be adequate (averages as well as
heuristics)
 Heuristic approaches are not even close to optimality
 Used in custom chip design
 One-hot encoding
 Easy for small state machines
 Generates small equations with easy to estimate complexity
 Common in FPGAs and other programmable logic
 Output-based encoding
 Ad hoc - no tools
 Most common approach taken by human designers
 Yields very small circuits for most FSMs
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 32
Sequential Logic Implementation Summary
 Implementation of sequential logic
State minimization
State assignment
 Implications for programmable logic devices
When logic is expensive and FFs are scarce, optimization is
highly desirable (e.g., gate logic, PLAs, etc.)
In Xilinx devices, logic is bountiful (4 and 5 variable TTs) and
FFs are many (2 per CLB), so optimization is not so crucial an
issue as in other forms of programmable logic
This makes sparse encodings like One-Hot worth considering
CS 150 - Fall 2005 – Lec #19: Seq Logic Optimization - 33