Transcript ECE 448 Review Session Practice final exam Solutions ECE 448 – FPGA and ASIC Design with VHDL George Mason University.

ECE 448
Review Session
Practice final exam
Solutions
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Part I
Problem 1
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
High-Level Languages
• C-Based System level languages
• Commercial
• SystemC -- The Open SystemC Initiative
• Handel C -- Celoxica Ltd.
• Impulse C -- Impulse Accelerated Technologies
• Research
• Streams-C -- Los Alamos National Laboratory
• SA-C -- Colorado State University, University of
California, Riverside, Khoral Research, Inc.
• SpecC – University of California, Irvine and
SpecC Technology Open Consortium
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Other High-Level Design Flows
• Matlab-based
• AccelChip DSP Synthesis -- AccelChip
• System Generator for DSP -- Xilinx
• GUI Data-Flow based
• Corefire -- Annapolis Microsystems
• Java-based
• Commercial
• Forge -- Xilinx
• Research
• JHDL – Brigham Young University
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Two major high-level language (HLL)
programming models
SRC 6 & SRC 7 from
SRC Computers
SRC MAP C programming model
Cray XD1 from
from Cray
Mitrion-C programming model
SGI Altix from
SGI
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Part I
Problem 2
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Most advanced reconfigurable
computing machines currently on the market
Machine
Released
SRC 6 from
SRC Computers
2002
Cray XD1 from
from Cray
2005
SGI Altix from
SGI
2005
SRC 7 from
SRC Computers, Inc,
2006
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Part I
Problem 3
ECE 448 – FPGA and ASIC Design with VHDL
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Introduction
• CAD tools provide several advantages
• Ability to evaluate complex conditions in which solving one
problem creates other problems
• Use analytical methods to assess the cost of a decision
• Use synthesis methods to help provide a solution
• Allows the process of proposing and analyzing solutions to occur
at the same time
• Electronic Design Automation
• Using CAD tools to create complex electronic designs (ECAD)
• Several companies who specialize in EDA
•
•
•
•
Synopsys®
Cadence® Design Systems
Magma® Design Automation Inc.
Mentor Graphics®
CAD Tools Allow Large Problems to be Solved
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Part I
Problem 4
ECE 448 – FPGA and ASIC Design with VHDL
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Wireload model basics (2)
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Wireload model basics (1)
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Part I
Problem 5
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Physical Verification
• Checks the design for fabrication feasibility and physical defects that
could result in the design to not function properly
• 3 checks (DRC, ERC, and LVS)
• Design Rule Checks (DRC)
• Verifies that design does not violate any fabrication rules
associated with the target process technology (metal width/space,
antenna ratio, etc)
• Electrical Rules Checks (ERC)
• Verifies that there are no short or open circuits with power and
ground as well as resistors/capacitors/transistors with floating
nodes (part of LVS)
• Layout Versus Schematic (LVS)
• Final physical design matches the logical (schematic) version in
terms of correct connectivity and number of electrical devices
Hercules™ is the Sign-Off Tool for Physical Verification
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Part I
Problem 6
ECE 448 – FPGA and ASIC Design with VHDL
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Technology File
• Layer and via Definitions
• Process design rules (Minimum metal widths and spacing)
• Resistance / Capacitance parasitic models
• Units (Time / Capacitance / Distance)
• GUI display information (Colors and fill template for layers)
• This file is stored in the design library (Common Database)
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Part I
Problem 7
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Xilinx Spartan-3 Block RAM
Port Aspect Ratios
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ECE 448 – FPGA and ASIC Design with VHDL
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Part I
Problem 8
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
ECE 448 – FPGA and ASIC Design with VHDL
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Part I
Problem 9
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
ECE 448 – FPGA and ASIC Design with VHDL
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Multi-Gigabit Transceivers
• Virtex-4 RocketIO™
• Full-duplex serial transceiver
blocks with integrated
SERDES and Clock and Data
Recovery
• 622 Mbps to >10 Gbps I/O
• Widest speed range
• Compatible with Virtex-II Pro
• Supports chip-to-chip,
backplane, chip-to-optics
SONET
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ECE 448 – FPGA and ASIC Design with VHDL
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Microprocessor & Ethernet
• Ethernet Media Access Controller
• EMAC with PowerPC
• PowerPC runs Protocol Stacks
• EMAC used to debug and control PPC or
EMAC
• PPC to configure and control the EMAC
PowerPC
• EMAC without PowerPC
405
• Any application with control state machine
EMAC
or soft processor in the FPGA fabric
• Two EMACs per PowerPC
Hard EMACs
• Redundancy
• Bridging
Hard Ethernet Controller saves 6000 slices
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Dedicated Circuits in FPGAs
• “Hard” cores offer density, speed, lower power
• Equal to 90-nm ASICs, but far less expensive
• Expandable, pipelined Multiplier/Accumulator
• Dual-ported BlockRAM with FIFO controller
• ChipSynch I/O serializer/ deserializer + IDELAY
• Multi-Gigabit transceivers, 0.6 to 11 Gbps
• PowerPC µProcessor and Ethernet controller
Dedicated circuits provide a big performance
boost
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Part I
Problem 10
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
ECE 448 – FPGA and ASIC Design with VHDL
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Part I
Problem 11
ECE 448 – FPGA and ASIC Design with VHDL
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Customary schematic for a PLA
x1
x2
x3
OR plane
P1
P2
P3
P4
AND plane
f1
ECE 448 – FPGA and ASIC Design with VHDL
f2
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Programmable Array Logic
x1
x2
x3
P1
f1
P2
P3
f2
P4
AND plane
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Part I
Problem 12
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
A generic structure of CPLD
(Complex Programmable Logic Device)
Programmable
Interconnect
matrix
Input/output pins
SPLD-like
blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Part I
Problem 13
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Frequency Synthesis
1.0 x original clock frequency
2.0 x original clock frequency
.5 x original clock frequency
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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DLL vs PLL
DLL is a rugged & reliable digital circuit
PLL is a more sensitive linear circuit
Voltage-controlled Oscillator needs clean supply
DLL has unavoidable jitter
PLL can reduce jitter,
But only if carefully designed and supplied
Frequency Multiplication is easier with PLL
PLL supply filtering can be very difficult
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Part I
Problem 14
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Reconfiguration Interfaces in Xilinx FPGAs
Internal Port
ICAP
(Virtex-II)
JTAG
SelectMap
(8 bits Parallel)
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Part I
Problem 15
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Feature
SRAM
Antifuse
E2PROM /
FLASH
Technology node
State-of-the-art
One or more
generations behind
One or more
generations behind
Reprogrammable
Yes
(in system)
No
Yes (in-system
or offline)
Reprogramming
speed (inc.
erasing)
Fast
----
3x slower
than SRAM
Volatile (must
be programmed
on power-up)
Yes
No
No
(but can be if required)
Requires external
configuration file
Yes
No
No
Good for
prototyping
Yes
(very good)
No
Yes
(reasonable)
Instant-on
No
Yes
Yes
IP Security
(especially when using
bitstream encryption)
Very Good
Very Good
Size of
configuration cell
Large
(six transistors)
Very small
Medium-small
(two transistors)
Power
consumption
Medium
Low
Medium
Rad Hard
No
Yes
Not really
Acceptable
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Part I
Problem 16
ECE 448 – FPGA and ASIC Design with VHDL
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Procedures – basic features
Procedures
• do not return a value
• are called using formal and actual parameters the same way
as components
• may modify parameters passed to them
• each parameter must have a mode: IN, OUT, INOUT
• parameters can be constants (including generics), signals
(including ports), and variables;
the default for inputs (mode in) is a constant, the default for
outputs (modes out and inout) is a variable
• when passing parameters, range specification should be
included (for example RANGE for INTEGERS, and
TO/DOWNTO for STD_LOGIC_VECTOR)
• Procedure calls are statements on their own
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Functions – basic features
Functions
• always return a single value as a result
• are called using formal and actual parameters the same way
as components
• never modify parameters passed to them
• parameters can only be constants (including generics)
and signals (including ports);
variables are not allowed; the default is a CONSTANT
• when passing parameters, no range specification should
be included (for example no RANGE for INTEGERS, or
TO/DOWNTO for STD_LOGIC_VECTOR)
• are always used in some expression, and not called on
their own
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Part I
Problem 17
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Typical locations of subprograms
PACKAGE
PACKAGE BODY
LIBRARY
global
FUNCTION /
PROCEDURE
ENTITY
local for all architectures
of a given entity
ARCHITECTURE
Declarative part
local for a given architecture
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Package containing a function (1)
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE specialFunctions IS
FUNCTION Pow( SIGNAL N: INTEGER; Exp : INTEGER)
RETURN INTEGER;
END specialFunctions
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Package containing a function (2)
PACKAGE BODY specialFunctions IS
FUNCTION Pow(SIGNAL N: INTEGER; Exp : INTEGER)
RETURN INTEGER IS
VARIABLE Result : INTEGER := 1;
BEGIN
FOR i IN 1 TO Exp LOOP
Result := Result * N;
END LOOP;
RETURN( Result );
END Pow;
END specialFunctions
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Part I
Problem 18
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Operator overloading
• Operator overloading allows different
argument types for a given operation
(function)
• The VHDL tools resolve which of these
functions to select based on the types of
the inputs
• This selection is transparent to the user as
long as the function has been defined for
the given argument types.
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Different declarations for the same operator Example
Declarations in the package ieee.std_logic_unsigned:
function “+” ( L: std_logic_vector;
R:std_logic_vector)
return std_logic_vector;
function “+” ( L: std_logic_vector;
R: integer)
return std_logic_vector;
function “+” ( L: std_logic_vector;
R:std_logic)
return std_logic_vector;
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