Transcript Logic Gates  Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding logic circuits in Integrated Circuit.

Logic Gates

Logic gates are electronic digital circuit
perform logic functions. Commonly expected
logic functions are already having the
corresponding logic circuits in Integrated
Circuit (I.C.) form.
Design of Circuit Procedures
1.
2.
3.
4.
5.
6.
7.
8.
9.
Obtain a precise circuit specification
Development of a truth table
Identifying the minterms corresponding to each
row in the table.
Drawing Karnaugh maps
Forming groups of 1's on the Karnough map
Writing the reduced expression
Converting the reduced expression into a realizable
expression
Drawing the circuit diagram
Construct and test a prototype circuit.
Types of Logic Gates
AND Gate
A
B
NAND Gate
C
OR Gate
A
B
A
B
C
NOR Gate
A
C
B
NOT Gate
Exclusive - OR Gate
A
A
C
A B=C
B
C
Basic Gates
AND , OR , NOT
AND Gate


The AND gate implements the Boolean AND function
where the output only is logical 1 when all inputs are
logical 1.
The standard symbol and the truth tabel for a two
input AND gate is:
Boolean expression of AND
The Boolean expression for the
AND gate is R=A.B
A
0
0
1
1
B
0
1
0
1
R
0
0
0
1
OR Gate


The OR gate implements the Boolean OR
function where the output is logical 1 when
just input is logical 1.
The standard symbol and the truth table for a
two input OR gate is:
Boolean Expression of OR
The Boolean expression for the
OR gate is: R=A+B
A
0
0
1
1
B
0
1
0
1
R
0
1
1
1
NOT Gate


The NOT gate implements the Boolean
NOT function where the output is the
inverse of the input.
The standard symbol and the truth
table for the NOT gate is:
Boolean Expression of NOT

The Boolean expression for the NOT
gate is: R=-A
A
R
0
1
0
0
Derived Gates
NAND , NOR , XOR
NAND Gate


The NAND gate is an AND gate followed by a NOT
gate. The output is logical 1 when one of the inputs
are logical 0
The standard symbol and the truth table for the
NAND gate is:
Boolean expression of NAND
A
0
0
1
1
B
0
1
0
1
R
1
1
1
0
NOR Gate


The NOR is a combination of an OR followed by a
NOT gate. The output is logical 1 when non of the
inputs are logical 0
The standard symbol and the truth table for the NOR
gate is:
Boolean Expression of NOR
A
0
0
1
1
B
0
1
0
1
R
1
0
0
0
XOR Gate


The XOR gate produces a logic 1 output only if its
two inputs are different. If the inputs are the
same, the output is a logic 0
The XOR symbol is a variation on the standard OR
symbol. It consists of a plus (+) sign with a circle
around it. The logic symbol, as shown here, is a
variation on the standard OR symbol.
Exercise 1
http://kom.auc.dk/logic/
De-Morgan’s Theorem and Logic
Conversion
1) ( A  B)  A  B
A
B
=
A
B
2) ( A  B)  A  B
A
B
=
A
B
C
3)
A
B
=
A
B
C
A B  A B  A  B
4) A  B  A  B  A  B
A
B
=
A
B
C
C
Implement the logic expression
using NAND gates only
1)
Z  X Y  Z
 X Y  Z
X
Y
Z
XYZ
 X Y  Z
2)
Z  XY  XZ  YZ
X
Y
 XY  XZ  YZ
X
Z
 XY  XZ  YZ
Y
Z
XY +XZ + YZ
Implement logic expression using
NOR gates only
1)
Z  (X Y) (X Y)
 (X Y) (X Y)
 X Y  X Y
X
Y
W
Revision Exercise




http://www.nottingham.ac.uk/~cczwoo
d/TestCourses/logic/logic-intro.html
http://www.cs.odu.edu/~jbollen/CS149/
demos.html
http://sandbox.mc.edu/~bennet/cs110/
boolalg/gate.html
http://www.cs.stedwards.edu/~jsnowde
/start.htm
Combinational Logic Designs

I1
In

A combinational logic circuit can be described by the
block schematic shown
:
:
Combinational
Logic
:
O1
:
On
Each output is a function of some or all of the input
variables, Hence
O1=f(I1,I2,....,In)
O2=f(I1,I2,…,In) ...
and On=f(I1,I2,…,In)
Half Adder
What is a Half adder?


Logic gate that perform addition for 1bit
When 1 + 1 occurs, a carry produce 1
Half Adder



Perform arithmetic additions
two inputs A, B to half-adder. Resultants are Sum(S)
and Carry(Cout)
A
S
H.A
B
Cout
Using K-Map to simplify the sum term, we get
S  A B  AB
 A B
C  AB
A
B
S
Cout
C S
B
A
0 0
0
0
0 1
1
0
0 1
0
1
1 0
1
1
Full Adder
What is Full Adder?



A full adder is a circuit that computes the sum
of three bits and gives a two-bit answer.
A circuit for adding two 16-bit numbers can
be built from 16 full-adder circuits. Each fulladder does one column of the sum.
The full adder for a given column adds two
bits from the input numbers together with a
one-bit carry from the previous column to the
right. The adder produces a two-bit answer;
one of these bits is used as a carry into the
next column.
A
B
Full Adder



Cin
Full
Adder
Cout
A full adder has 3 inputs and 2 outputs
The truth table of the full-adder can be
drawn with inputs A,B and Cin with outputs S and Cout
From the truth table we can write the Boolean equation for the
S and Cout
S  A B Cin  A BC in  AB C in  ABCin
Cout  A BCin  AB Cin  ABC in  ABCin

S
Simplify using Boolean Algebra and K-map, we get
S  A  B  Cin
Cout  ACin  BCin  AB
Sum = Any 2 of the three inputs are 1
Cout = XOR between A, B, Cin
A
0
0
0
0
1
1
B
0
0
1
1
0
0
Cin
0
1
0
1
0
1
Sum
0
0
0
1
0
1
Cout
0
1
1
0
1
0
1
1
1
1
0
1
1
1
0
1
Full Adder diagram
Half Subtractor
What is a Half Subtractor


A logic gate that perform 1 bit
subtraction
When 0-1 occurs, a carry produces 1
Half Subtractor
A0
B0
A0 B0 D0 C 1
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
1 2
0
-1
1
D0
C1
Half Subtractor

Operation: A - B
A
D
HS
D  A B  AB
Bout  A B
Bout
B
B
D
B
A
0
0
0
0
1
1
1
0
0
1
0
1
0
0
1
1
tuo
Full Subtractor
What is a Full Subtraction?

Logic gates that perform two bits
subtraction
Full Subtractor
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
AiBi
00
Ci
11
1
0
1
01
10
1
1
1
Di
Di = Ci $ (Ai $ Bi)
Same as Si in full adder
Full Subtractor
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
AiBi
00
Ci
11
10
1
0
1
01
1
1
1
Ci+1
Ci+1 = !Ai & Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi
Full Subtractor
Ci+1 = !Ai & Bi
# Ci & !Ai & !Bi
# Ci & Ai & Bi
Ci+1 = !Ai & Bi
# Ci & (!Ai & !Bi # Ai & Bi)
Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)
Recall:
Di = Ci $ (Ai $ Bi)
Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)
Full Subtractor
Di = Ci $ (Ai $ Bi)
Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)
Ci
Ai
Di
Bi
half subtractor
half subtractor
C i+1
Full Subtractor

Operation: A - B - Bin
tuo
B D
n iB
B
A
0
0
0
0
0
D  A B Bin  A BB in  ABBin  AB B in
1
1
1
0
0
Bout  A Bin  A B  BBin
1
1
0
1
0
1
0
1
1
0
D
0
1
0
0
1
Bout
0
0
1
0
1
0
0
0
1
1
1
1
1
1
1
A
B
Bin
FS
Adder/Subtractor - 1
A0
B0
S0
C1
A0
B0
D0
C1
Half subtractor
Half adder
A0
B0
SD0
E
CB1
E = 0: Half adder
E = 1: Half subtractor
Adder/Subtractor-1
Ci
Di
Ai
Bi
Ci+1
E
E = 0: Full adder
E = 1: Full subtractor
Full Adder
Reordered
Full Adder
Full
Subtractor
Ci Ai Bi Si Ci+1
Ci Ai Bi Si Ci+1
Ci Ai Bi Di Ci+1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
0
NOT
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
Making a full subtractor
from a full adder
Bi
Ai
C i+1
Full Adder
Di
Ci
Four-Bit Parallel Adder
A3
Carry
Out
C3
F.A3
S3



A2
B3
C2
B2
F.A2
S2
A1
C2
B1
A0
F.A1
C0
S1
B0
F.A0
S0
This circuit is sometimes referred to as a ripplethrough adder
C0 ripples through four two-level logic circuits and
hence the sum cannot be completed until eight gate
delays
For this kind of adder, the maximum delay is directly
proportional to the number of stages n.
Adder/Subtractor-2
A3
B3
A2
B2
A1
B1
A0 B 0
E
Full Adder
C3
C4
SD3
Full Adder
Full Adder
C2
SD2
Full Adder
C1
SD1
E = 0: 4-bit adder
E = 1: 4-bit subtractor
SD0
Carry Look-Ahead Circuit

To improve the speed of addition

Consider the carry output equation for a full adder is
Cout  A BCin  AB Cin  ABC in  ABCin

Which can be expressed as follows

Cout  ( A  B)Cin  AB
or as Cout  PC in  G

where P  A  B
G  AB
Carry Look-Ahead Circuit


Four a four-bit adder the generate and propagate
terms for each stage are G 0  A0  B 0 P 0  A0  B 0
G1  A1  B1 P1  A1  B1
G 2  A2  B 2 P 2  A2  B 2
G 3  A3  B 3 P 3  A3  B 3
while the carries for the various stages are
C 0  P0  C  1  G 0
C1  P1  C 0  G1
C 2  P 2  C1  G 2
C 3  P3  C 2  G 3
Carry Look-Ahead Circuit


Substituting for C0 in the C1 equation etc leads to the
following equations: C1  P1P 0C  1  P1G 0  G1
C 2  P 2 ( P1P 0C  1  P1G 0  G1)  G 2
And the sum
C 3  P3( P 2 ( P1P 0C  1  P1G 0  G1))  G 3
S 0  A0  B 0  C  1  P 0  C  1
S 1  P1  C 0
S 2  P 2  C1
S 3  P3  C 2

Since the number of levels of logic required when a
large number of bits has to be added does not
increase then the Carry Look-Ahead adder will
provide a faster addition time
Binary Multiplication


A2
B2
Paper and Pen method
which is implemented using
A2 B1
9 AND gates, 3 FA and
A2 B 2 A1B 2
3 HA
C 3 C 2
C 4 C 3
C 2
P5
P4
P3
A1
B1
A0
B0
A2 B 0 A1B 0 A0 B 0
A1B1 A0 B1
A0 B 2
C1
P2
P1
P0