Transcript Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst GITHU Processor   General Purpose 32-bit, pipelined computer processor MIPS-like architecture –   Reduced instruction set 16-bit address space 16

Group Number One
GITHU Processor
Tom Bozic
Ian Nuber
Greg Ramsey
Henry Romero
Matt Unangst
GITHU Processor


General Purpose 32-bit, pipelined computer
processor
MIPS-like architecture
–


Reduced instruction set
16-bit address space
16 Registers
–
–
R0 = 0
R15 = return address
Data/Address
Ribbon Cable
Ribbon Cable
RAM
ROM
Level
Shift
I/O
Ribbon Cable
LCD
Interrupt
Controller /
Chip Select
FPGA
Key Pad
Level
Shift
Interrupt Data
Ribbon Cable
Ribbon Cable
Keyboard
In
Monitor
Out
UART
Instruction Set Architecture

First two bits indicate instruction category
–


16 bit immediate built into R-type reduces complexity
of design
Addressing Modes
–
–

Load, store, bra/jump, R-type
Direct
Indirect with Offset
ISA accounts for full address space
–
NO PC-relative addressing
Instruction Format
Load / Store
31 30 29
Op(2)
24 23
Addr(6)
20 19
Rt (4)
16 15
0
Rs (4)
Address Displacement (16)
R-Type
31 30 29
Op (2)
25
Funct (5)
24
Imm (1)
23 20 19
Rd (4)
16 15
Rs1 (4)
12 11
Rs2 (4)
0
Immediate (12)
Bra / Jmp
31 30 29
Op(2)
26 25
Type(4)
24 23
Addr (2)
20 19
Rs (4)
0
Address Continued (20)
Load/Store Instructions (Op = 00/01)
Instruction
Assembly
Meaning
Ld
Ld 0[r3], r2
R2  Mem(r3)
St
St r4, 4[r3]
R4  Mem(r3 + 4)
R-Type Instructions (OP = 10)
Instruction
Function
Immed
Assembly Ex
Meaning (** = bitwise op)
Add
00000
0
Add r2, r3, r4
R2 = R3 + R4
Addi
00000
1
Addi r2, r2, 5
R2 = R2 + 5
Sub
00001
0
Sub r6, r3, r5
R6 = R3 – R5
Subi
00001
1
Subi r3, r4, 3
R3 = R4 – 3
And
00100
0
And r3, r2, r8
R3 = R2 & R8 **
Andi
00100
1
Andi r4, r4, 255
R4 = R4 & 0xFF **
Or
00110
0
Or r2, r3, r4
R2 = R3 | R4 **
Ori
00110
1
Ori r2, r8, 10
R2 = R8 | 0xA **
Nand
00101
0
Nand r3, r5, r9
R3 = !(R5 & R9) **
Nor
00111
0
Nor r2, r1, r4
R2 = !(R1 | R4) **
Xor
10010
0
Xor r3, r4, r5
R3 = R4 ! R5
Mult
11000
0
Mult r2, r3, r4
R2 = R3 * R4
Div
11100
0
Div r4, r5, r2
R4 = R5 / R2
R-Type Instructions (Cont’d)
Instruction
Function
Immed
Assembly Ex
Meaning (** = bitwise op)
Sll
01000
0
Sll r2, r2, r3
R2 = [R2] << R3
Slr
01001
0
Slr r2, r2, r3
R2 = [R2] >> R3
Sal
01010
0
Sal r4, r4, r3
R2 = [R4] << R3
Sar
01011
0
Sar r4, r4, r3
R2 = [R4] >> R3
Scl
01100
0
Scl r4, r4, 1
Circular shift left
Scr
01101
0
Scr r3, r3, 1
Circular shift right
Slt
10000
0
Slt r2, r3, r4
R2 =1 IF R3<R4, ELSE R2 = 0
Nop
11111
0
Nop
Insert Stall
Bra/Jmp Instructions (Op = 11)
Instruction
Type
Assembly
Meaning
Beq
0001
Beq r2, loop
IF r2 == 0, go to loop
Bne
0010
Bne r3, loop
IF r3 != 0, go to loop
Jmp
0100
Jmp main
Jump to “main”
Jpr
0110
Jpr r3
Jmp to addr. In r3
Jsr
1000
Jsr sub
Jump to sub, save PC
Hardware
Data Path Diagram
RAM – Read Access
RAM – Write Access
ROM – Timing Diagram
LCD – Display Timing
Parts List
Item
Quantity
Xilinx XCV400 FPGA (Virtex)
1
Flash Memory
2
SRAM
1
Perf Board
1
Level Shifters
5
Ribbon Cable (and headers)
4
Dip Sockets
8
4 x 20 LCD screen
1
16 button Keypad
1
Remaining Individuals Roles

Tom Bozic
–

Ian Nuber
–

Memory system design (RAM, ROM), PCB design
Henry Romero
–

Maintain Assembler, Interrupt handler, program design
Greg Ramsey
–

Control logic, documentation, Interrupt Controller
PCB design, peripheral integration
Matt Unangst
–
–
Pipeline implementation (forwarding, rollback)
Design integration oversight
Milestone 1

Pipeline implemented
–




Thoroughly tested
First PCB rev completed
Successful integration of processor, I/O,
Memory
Test program(s) written
User’s Manual near completion
Milestone 2

FINAL PRODUCT COMPLETE
–





Allows room for unexpected errors
Forwarding Path’s implemented in pipeline
Final PCB rev completed, implemented
Full integration of processor, I/O, memory
Demo program completed
Complete documentation
Schedule
Questions?