Transcript Lecture #26 Gate delays, MOS logic Today: • Gate delays • Another look at CMOS logic transistors 11/1/2004 EE 42 fall 2004 lecture 26

Lecture #26 Gate delays, MOS logic
Today:
• Gate delays
• Another look at CMOS logic transistors
11/1/2004
EE 42 fall 2004 lecture 26
1
Controlled Switch Model of Inverter
VOUT
VDD = 3V
Output when:
VIN =3V
RN
V-SS = 0V
+
VOUT
-
RP
+
VOUT
V-SS = 0V
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3
0
VDD = 3V
VIN =0V
VIN jumps from
3V to 0V
-
VIN jumps from
0V to 3V
tD
t
What is the gate delay tD
for this simple inverter?
If we define tD as the time to
go halfway to the asymtotic
limit, tD = 0.69RC . To get
equal delays we will need to
set RP = RN.
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2
Simple model for logic delays (slide 2 again)
We model actual logic gate as an ideal logic gate fed by an RC
network which represents the dominant R and C in the gate.
R
v IN ( t )
Ideal
Logic
gate
VX
C
Model of Actual
Logic Gate
v OUT ( t )
vIN
vOUT
VX
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v OUT ( t )
Ideal
Logic
gate
etc.
This model is very close to real
physics: the transistors are
inherently extremely fast, but are
slowed by the need to charge up
(or discharge) the capacitance at
the various nodes.
t
tD = 0. 69 RC
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3
NMOS and
PMOS use the
same set of
input signals
CMOS Logic Gate
VDD
PMOS only in pull-up
PMOS conduct when input is low
A
B
PMOS do not conduct when
A +(BC)
C
VOUT
NMOS only in pull-down
B
A
NMOS conduct when input is high.
NMOS conduct for A + (BC)
C
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Logic is Complementary and
produces F = A + (BC)
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4
CMOS Logic Gate: Example Inputs
VDD
A=0
B=0
C=0
PMOS all conduct
A
Output is High
B
C
VOUT
B
= VDD
NMOS do not conduct
A
C
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Logic is Complementary and
produces F = 1
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CMOS Logic Gate: Example Inputs
VDD
A=0
B=1
C=1
PMOS A conducts; B and C Open
A
Output is High
B
C
VOUT
B
=0
NMOS B and C conduct; A open
A
C
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Logic is Complementary and
produces F = 0
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6
Switched Equivalent Resistance
Network V
VDD
DD
RU
A
A
RU
RU
B
C
VOUT
C
B
Switches
close when
input is low.
VOUT
RD
B
A
RD
B
A
RD
C
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Switches
close when
input is high.
C
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Logic Gate Propagation Delay: Initial
State
VDD
The initial state depends on the old (previous) inputs.
RU
A
RU
RU
C
B
VOUT
RD
RD
The equivalent resistance of the pull-down or pullup network for the transient phase depends on the
new (present) input state.
B
A
RD
Example: A=0, B=0, C=0 for a long
time.
These inputs provided a path to VDD
for a long time and the capacitor has
charged up to VDD = 5V.
COUT = 50 fF
C
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Logic Gate Propagation Delay: Transient
VDD
At t=0, B and C switch from low to
high (VDD) and A remains low.
RU
A
RU
RU
And opens a path from VOUT to GND
C
B
VOUT
RD
RD
COUT discharges through the pull-down
resistance of gates B and C in series.
B
A
RD
C
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This breaks the path from VOUT to VDD
COUT = 50 fF
Dt = 0.69(RDB+RDC)COUT
= 0.69(20kW)(50fF) = 690 ps
The propagation delay is
two times longer than that
for the inverter!
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9
Logic Gate: Worst Case Scenarios
VDD
What combination of previous and
present logic inputs will make the
Pull-Up the fastest?
RU
A
RU
RU
C
B
VOUT
RD
RD
B
A
RD
C
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What combination of previous and
present logic inputs will make the
Pull-Up the slowest?
What combination of previous and
present logic inputs will make the
Pull-Down the fastest?
COUT = 50 fF
What combination of previous and
present logic inputs will make the
Pull-Down the slowest?
EE 42 fall 2004 lecture 26
Fastest
overall?
Slowest
overall?
10
MOS transistors
• The heart of digital logic is the MOS
transistor, both NMOS and PMOS
• In the next couple of lectures, we will learn
more about how CMOS logic works at the
circuit level,
• starting with a review of the NMOS
transistor
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NMOS TRANSISTOR STRUCTURE
“Metal” gate (Al or
Si)
• NMOS = N-channel
Metal Oxide Silicon
Transistor
• An insulated gate is placed above the silicon
• Its purpose is to control the current between n-type regions (by
inducing a “channel” of electrons when a positive V is applied).
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MOS TRANSISTOR STRUCTURE
DEVICE IN CROSS-SECTION
“Metal”
“Oxide”
“Semiconductor”
G
“Metal” gate (Al or Si)
D
S
gate
oxide insulator
n
n
P
• The “gate” electrode is just a conductor to act as the capacitor top plate
• The lower “body” electrode is silicon with almost no electrons present
(essentially an insulator)
• Thus no current can flow between the D and S electrodes which contact
the silicon
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MOS TRANSISTOR STRUCTURE
DEVICE with + Gate Voltage
S
+
5V
n
G
“Metal” gate (Al or Si)
++++++++++++
_ _ _oxide
_ _ _insulator
______
D
n
P
• Here the 5V across the capacitor induces + charge on the gate and – charge
on the surface of the semiconductor, according to Q=CV.
• The charge in the semiconductor is really just free electrons which can
carry current (just like the electrons in a metal can carry current).
• Thus by applying a voltage to the gate we have provided a conduction
path for current if a voltage is applied from D to S.
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MOS Transistor as a controlled switch
VGS
+

S
iD VGS >> VT
i
G
D
VGS > VT
oxide
Si
tox
+
 VDS
iD Zero if VGS is
small V
DS
But the device is not fundamentally ON/OFF. As VGS increases, the
switch resistance decreases (slope becomes steeper).
Thus we have a “family of I-V curves” which describe the current into D
as a function of both VDS and VGS
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Three-Terminal Device Graphs
ID (mA)
ID
3-Terminal
Device
G
VGS
D
10
ID versus VDS for VGS = 2V.
+
S
Concept of 3-Terminal Device Graphs:
1
2
VDS (V)
We set a voltage (or current) at one set of
terminals (here we will apply a fixed VGS of 2V)
and conceptually draw a box around the device
with only two terminals emerging
So we can now plot the two-terminal
characteristic (here ID versus VDS).
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Three-Terminal Parametric Graphs
ID
3-Terminal
Device
G
VGS
ID (mA)
D
10
+
-
VGS = 3
VGS = 2
VGS = 1
S
Concept of 3-Terminal Parametric Graphs:
1
2
VDS (V)
We set a voltage (or current) at one set of
terminals (here we will apply a fixed VGS)
and conceptually draw a box around the device
with only two terminals emerging so we can
again plot the two-terminal characteristic (here
ID versus VDS).
But we can do this for a variety of values of VGS
with
the result that we get a family
curves.
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NMOS I vs V Characteristics
Example of experimental I-V characteristics. (You can do in the 43 Lab)
ID
S
VGS
+

G
iD
D
VDS
+

VGS
VGS = 2
VGS = 1.5
VGS = 1
VGS = 0
VDS
For low gate voltages, no drain current flows. As VGS is increased
above threshold, e.g. 1V, the nonlinear “saturating” I-V curve is
obtained. Increasing VGS causes ID to increase, as the family of curves
indicates.
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The Family of ID vs VGS Curves
For short-channel devices used in digital logic, the ID vs VDS curves
are decidedly nonlinear! Curves which start out as simple linear
resistors saturate as shown on this and the previous slide.
We can approximate the I-V
characteristics as two straight
lines.
a) the linear “resistance”
region at low VDS and
b) the saturation region
(almost horizontal) at
larger VDS.
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ID(mA)
1.25
VGS  VT  1V
4
3
2
1
0.75
0.5
0
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0.5
VDS
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NMOS Summary
ID
ID
D
IDS
G
ID for VGS = maximum (VDD)
N Ch
S
If VGS = 0.
The circuit symbol
VDS
VDD
D
A value for RDN is chosen to
give the correct timing delay.
RDN
G
S
Electrical Model
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Remember the Role of the Switch
VIN
The NMOS transistor conducts the charge out of the capacitor
to ground when its input (VGS) is high (VDD).
VDD = 3V
We cover up the non-useful parts
of the circuit for simplicity.
G
D
=3V
+ The capacitor was initially at 3V
VOUT (VDD), and goes toward zero. We
RN
define one stage delay by the time for
S
- VOUT = VDS to reach 1.5V (VDD /2).
- SS = 0V
V
ID
Now lets draw the I-V
VGS = VDD
characteristics of the NMOS
IDS
When VGS jumps to VDD, the current
jumps from zero to this value.
VGS = 0
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VDD/2
VDD
As the capacitor discharges, V decreases
and the current follows the IDS vs VDS
VDS curve. As a first approximation we will
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26 l=0
21
Computing the stage delay
The stage delay is the time for VOUT to decrease from VDD to VDD /2.
G
+
VIN =3V
-
D
C
RN
-
+
VOUT
-
S
ID
VGS = VDD
τ   (C I )dV  (C I )V /2
AV
IDS
AV
DD
=CVDD/2IDS for l = 0
VGS = 0
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The capacitor is initially charged to 3V,
and we want to see how long it takes to
reach 1.5V. That is the delay.
As V goes from VDD to VDD /2, the
average current IAV  IDS( 1+lX(3/4)VDD)
( IDS if l is close to zero; consider this
case first).
We integrate the capacitor equation
I  C dV dt to find the time:
VDD/2
VDD
VDS
As the capacitor discharges, V
decreases and the current
follows the IDS vs VDS curve.
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Computing the stage delay (for l 0)
The stage delay t is the time for VOUT to decrease from VDD to VDD /2.
Thus t = CVDD/2IDS for l = 0
G
+
VIN =3V
-
D
C
RN
-
OUT
-
S
ID
IDS
+
V
VGS = VDD
We would compute t = 0.69RC = 0.69 (3VDD/4IDS )C
That is t = 0.52 CVDD/IDS which is only 4% larger
than the value we found by doing the actual
integration.
Here we approximate l = 0 so
the slope is zero
VGS = 0
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VDD/2
Now suppose we had instead assumed
a resistance which averaged VDD/IDS and
VDD/2IDS ,that is 3VDD/4IDS , shown as the
blue line in the figure below.
VDD
VDS
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Computing the stage delay (for l >0)
We found by integration that τ   (C I AV )dV  (C I AV )VDD /2
G
+
VIN =3V
-
D
C
RN
-
+
VOUT
Since IAV  IDS( 1+lX(3/4)VDD) we have t
=0.5C VDD / IDS( 1+lX(3/4)VDD). Now lets
compare with the value we would get using
an averaged-value resistor (blue line below)
-
S
As VOUT goes from VDD to VDD /2, the average
resistance is (3/4) VDD / IDS( 1+lX(3/4)VDD)
thus our time constant (0.69RC) equals
ID
VGS = VDD
IDS
Again, this is only 4% different from the
answer obtained by direct integration
As the capacitor discharges, VOUT decreases
and the current follows the IDS vs VDS curve.
VGS = 0
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t=0.69 C (3/4) VDD / IDS( 1+lX(3/4)VDD)
= 0.52 C VDD / IDS ( 1+lX(3/4)VDD)
VDD/2
VDD
VDS
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Computing the stage delay - Summary
G
+
VIN =3V
-
D
C
RN
-
+
VOUT
-
S
During the discharge of C through the NMOS
transistor, we have shown that we can
compute the stage delay t by using the
switch model with an effective resistance
RDN = (3/4) VDD / IDS( 1+lX(3/4)VDD)
Thus we can compute the stage delay,
0.69RDNC,
IDS ( 1+lVDD)
ID
VGS = VDD
D
IDS
RDN
G
VGS = 0
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VDD/2
VDD
VDS
S
Electrical Model
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