Transcript InP HBTs: Process Technologies and Integrated Circuits Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-3262 fax.

InP HBTs:
Process Technologies and Integrated Circuits
Mark Rodwell
University of California, Santa Barbara
[email protected] 805-893-3244, 805-893-3262 fax
Acknowledgments
Collaborators
Prof. A. Gossard, Dr. A. Jackson, Mr. J. English Materials Dept., University of California, Santa Barbara
M. Urteaga, R. Pierson , P. Rowell, B. Brar Rockwell Scientific Company
Lorene Samoska, Andy Fung Jet Propulsion Laboratories
S. Lee, N. Nguyen, and C. Nguyen Global Communication Semiconductors
Prof. Suzanne Mohney and Group, Penn State
Prof. Ian Harrison, Univ. Nottingham
Present HBT Team Members
Z. Griffith, C. Kadow, N. Parthasarathy, U. Singisetti, C. Sheldon
Past HBT Team Members (random order)
V. Paidi, D. Scott, Y. Dong, M. Dahlström, Y. Wei, M. Urteaga, L. Samoska, S. Lee, Y.-M. Kim, Y. Betser, D. Mensa,
U. Bhattacharya, PK Sundararajan, S. Jaganathan, J. Guthrie, H-J. Kim, R. Pullela, B. Agarwal, Q. Lee.
Sponsors
US DARPA: John Zolper, Steve Pappert
US ONR: Dan Purdy, Ingham Mack, Max Yoder
US ARO,
JPL presidents fund, Agilent Technologies, Sun Microsystems, Walsin Lihwa
Thanks To Prof. Bill Frensley, UT Dallas, for the use of BandProf
Applications
High Frequency Electronics: Applications
Optical Fiber Transmission
40 Gb/s InP HBT fiber chip set (Gtran Inc.)
40 Gb/s: InP and SiGe ICs commercially available
80 & 160 Gb/s is feasible
80-160 Gb/s InP ICs now clearly feasible
~100 GHz modulators demonstrated (KTH Stockholm)
100 + GHz photodiodes demonstrated in 1980's
challenge: limit to range due to fiber dispersion
challenge: competition with WDM using 10 Gb CMOS ICs
250 GHz digital radio: 100 Gb/s over 1 km in heavy rain
Radio-wave Transmission / Radar / Imaging
65-80 GHz, 120-160 GHz, 220-300 GHz
100 Gb/s transmission over 1 km in heavy rain
300 GHz imaging for foul-weather aviation
mm-wave sensor networks
300 GHz imaging
science
spectroscopy, radio astronomy
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs, DACs
high resolution at very high bandwidths sought
Gb/s Wireless Home Networks
Fast IC Technologies
InP HBT: 500 nm emitter
455 GHz ft / 485 GHz fmax
~4 V breakdown
150 GHz static dividers
178 GHz amplifiers
SiGe HBT: 130 nm emitter
300 GHz ft / 350 GHz fmax
96 GHz static dividers
77 GHz amplifiers
150 GHz push-push VCO- 75 GHz fundamental
CMOS: 90 nm node:
~200 GHz ft / 250 GHz fmax
~1-1.5 V breakdown
60 GHz 2:1 mux
91 GHz amplifiers
InP HBTs as ultra high speed technology:
~500 GHz bandwidth even at 500 nm scaling with minimal parasitic reduction
Potential for much wider bandwidths at ~100 nm scaling
InP HBTs for radio astronomy
feasibility of 100 mW power amplifiers at 200 GHz & perhaps 300 GHz
→ aid in developing THz diode frequency multiplier chains
InP DHBTs for 33 / 45 / 60 / 77 / . . . / 94 GHz power ?
InP HBTs have
the necessary bandwidth
InP HBTs can handle
the necessary voltage
10 V breakdown → adequate power
370 GHz HBTs have 5.6 V breakdown
200 GHz (W-band) HBTs will have 10 V
W-band amps need 200 GHz ft & fmax
Today's InP HBTs: 400-500 GHz ft & fmax
H
max
f
t
300
200
21
20
cb
2
I = 13.2 mA
= 0.6 V
3
4
5
J (mA/um 2)
6
e
c
jbe
10
2
= 0.6 x 4.25 um
e
A
2
8
V
1
15
HBT with pedestal
HBT without pedestal
10
400
20 mW/m
device failure
2
25
GHz
U
30
Gains (dB)
f
500
J (mA/m )
35
6
4
2
J = 5.17 mA/um , V = 0.6 V
e
5
f = 391 GHz, f
t
0
max
A = 0.4 x 7 m
2
cb
2
je
I step = 500 A
= 505 GHz
b
0
9
10
10
11
12
10
10
Frequency (Hz)
10
0
1
2
V
3
(V)
4
5
6
ce
InP HBTs can handle
the necessary power density
10 mW/um2 DC dissipation is reliable
→ 5 mW/um2 RF output power
→ 2.5 mW/um in 0.5 um technology
2 THz-Volt breakdown-bandwidth product
EmaxVsat=2*1013 Volt/second
5
10 mW/m
2
18 mW/m
2
→ Power amplifiers to ~80 GHz in 1 um processes
1 um GaAs HBT processes are cheap, why not so InP ?
e
2
J (mA/m )
4
3
loadline
2
→ Power amplifiers to ~350 GHz in 250 nm processes
mm-wave & sub-mm-wave systems for radio astronomy
1
0
0
2
4
6
V (V)
ce
8
10
HBT technology
Indium Phosphide Heterojunction Bipolar Transistors
Z. Griffith
epitaxial layer designs
PK Sundararajan
DHBT epitaxy: Graded InAlAs Emitter, InGaAs base, InAlGaAs Grades
InAlAs emitter
InAlAs/InGaAs CSL grade
bandgap-graded InGaAs base
InAlAs/InGaAs CSL grade
InP collector
high breakdown
important for microwave power
important for logic
low thermal resistance
necessary for high power density
essential for microwave power
essential for logic
Layer
Material
Doping
Thickness (Å)
Emitter cap
In0.53Ga0.47As
2  1019 cm-3: Si
300
N+ emitter
InP
2  1019 cm-3: Si
700
N- emitter
InP
8  1017 cm-3: Si
500
Emitter-base
grade
In0.53Ga0.26Al0.21As
to In0.455Ga0.545As
P: 4  1017 cm-3: Si
N: 8  1017 cm-3: C
233
47
Base
In0.53Ga0.47As
N: 4  1019 cm-3: C
400
Basecollector
grade
In0.53Ga0.47As
to In0.53Ga0.26Al0.21As
N: 2  1016 cm-3: Si
240
Pulse doping
InP
5.6  1018 cm-3: Si
30
Collector
InP
N: 2 1016 cm-3: Si
1,630
Subcollector
InP
N: 1 1019 cm-3: Si
~1000 Å
Performance
ft and fmax good or better than SHBTs
emitter
collector
emitter
cap
graded
base
subcollector
DHBT epitaxy: Abrupt InP Emitter, InGaAs base, InAlGaAs C/B Grade
InGaAs 3E19 Si 400 Å
Vbe = 0.75 V, Vce = 1.3 V
Emitter
InP 3E19 Si 800 Å
InP 8E17 Si 100 Å
InP 3E17 Si 300 Å
InGaAs 8E19  5E19 C 300 Å
Base
Setback 3E16 Si 200 Å
Collector
Grade 3E16 Si 240 Å
InP 3E18 Si 30 Å
InP 3E16 Si 1030 Å
InP 1.5E19 Si 500 Å
InGaAs 2E19 Si 125 Å
InP 3E19 Si 3000 Å
SI-InP substrate
Key Features:
• Abrupt InP emitter—benefit unclear
• Collector setback—eases grade design
• Thin InGaAs in subcollector—remove heat
• Thick InP subcollector—decrease Rc,sheet
Other InP DHBT Layer Structures
InGaAs/InGaAsP/InP grade
InP/GaAsSb/InP DHBT
IEDM 2001
-suitable for MOCVD growth
- excellent results
- does not need B/C grading
- E/B band alignment through
GaAsSb alloy ratio (strain)
or InAlAs emitter
- somewhat poorer transport parameters
to date for GaAsSb base
Single-HBTs: InGaAs base and InGaAs collector
low breakdown:
scaling beyond ~75 GHz
digital clock rate very difficult
high collector-base leakage
particularly at elevated temperatures.
Serious difficulties in real applications
very high thermal resistance
InGaAs collector and subcollector
can reduce with InP subcollector
limits power density
limits both digital and mm-wave application
Dino Mensa
Layer
Material
Doping
Thickness (Å)
Emitter cap
In0.53Ga0.47As
2  1019 cm-3: Si
300
N+ emitter
InP
2  1019 cm-3: Si
700
N- emitter
InP
8  1017 cm-3: Si
500
Emitter-base
grade
In0.53Ga0.26Al0.21As
to In0.455Ga0.545As
P: 4  1017 cm-3: Si
N: 8  1017 cm-3: C
233
47
Base
In0.53Ga0.47As
N: 4  1019 cm-3: C
400
Collector
In0.53Ga0.47As
N: 2 1016 cm-3: Si
2000
Subcollector
InP
N: 1 1019 cm-3: Si
~1000 Å
process flow
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
Z. Griffith
PK Sundararajan
Basic Mesa IC Process
• Both junctions defined by selective
wet-etch chemistry
• Narrow base mesa allows for low
AC to AE ratio
• Low base contact resistance—
Pd based ohmics with C < 10-7 ∙cm2
• Collector contact metal and metal ‘1’
used as interconnect metal
• Microstrip wiring environment….
• NiCr thin film resistors = 40  / 
• has predictable characteristic impedance
• MIM capacitor, with SiN dielectric…
-- used only for bypass capacitors
• controlled-impedance interconnects
within dense mixed signal IC’s
• Low loss, low r = 2.7 microstrip wiring
environment
• ground plane eliminates signal coupling
that occurs through on-wafer gnd-return
inductance
Completed mesa HBTs
& ICs
Mesa Process -- Without Passives & Interconnects
Z. Griffith
PK Sundararajan
End view
Top view
Side view
9200 Ǻ
4600 Ǻ
4200 Ǻ
1.20 m
Mesa Process -- With Passives & Interconnects
Process front end
• transistors, resistors, and M1 interconnects
Process back end
• capacitors, M2, and ground plane formation (M3)
Z. Griffith
PK Sundararajan
Zach Griffith
Mesa Process -- Some Pictures
Transistor
Figures of Merit
Short-circuit current-gain cutoff frequency
Rgen
Vgen
1
H 21 ( f ) 
1 /     jf / ft 
35
h
30
21
25
Gains (dB)
Iin
Iout
short-circuit current gain:
drive input, short output,
measure H21=Iout/Iin
20
2
15
A
10
I = 20.6 mA, V = 1.53 V
jbe
= 0.6 x 4.3 um
c
ce
2
J = 8.0 mA/um , V = 0.6 V
e
5
cb
f = 450 GHz, f
t
max
= 490 GHz
0
9
10
10
10
10
Frequency (Hz)
11
10
12
Current-gain cutoff frequency in HBTs
 kT

1
kT
 t base  t collector  C je
 Cbc 
 Rex  Rcoll 
2ft
qIE
 qIE

t base  Tb2 2Dn
t collector  Tc 2veff
RC terms are quite important for high bandwidth devices
...layers can always be thinned until RC terms dominate !
Miguel Urteaga
Definition of power gains and fmax
MSG/MAG is of direct relevance in tuned RF amplifier design
Maximum Available Gain
Simultaneously match input and
output of device
MAG 
S21
S12
K 
K 1
2
g e ne ra tor
loa d
R ge n

Vg e n
los s le s s
m a tc hin g
n e two rk
los s le s s
ma tc h in g
ne two rk
RL
K = Rollet stability factor
Transistor must be unconditionally stable or MAG does not exist
Maximum Stable Gain
Stabilize transistor and simultaneously
match input and output of device
g e ne ra tor
R ge n
Vg e n
MS G 
S21
S12

Y21
Y12

1
ωCcb  R ex  kT 
qI c 

Approximate value for hybrid- model
To first order MSG does not
depend on ft or Rbb
loa d
los s le s s
m a tc hin g
n e two rk
re s is tive
los s
(s ta b iliz a tio n)
los s le s s
ma tc h in g
ne two rk
RL
For Hybrid-  model, MSG rolls off at
10 dB/decade, while MAG has no fixed slope.
So, NEITHER can be used to accurately
extrapolate fmax
Miguel Urteaga
Unilateral Power Gain
Mason’s Unilateral Power Gain
Use lossless reactive feedback to cancel
device feedback and stabilize the device,
then match input/output.
U
Y21  Y12
s h un t
fe e d b a c k
g e n e ra to r
R ge n
lo a d
lo s s le s s
m a tc h in g
n e tw o rk
Vge n
2
lo s s le s s
m a tc h in g
n e tw o rk
RL
s e rie s
fe e d b a c k
4G11G 22  G 21G12 
40
U is not changed by pad reactances
U: all 3
35
For Hybrid-  model,
U rolls off at 20 dB/decade
ALL Power Gains must be unity at fmax
Gains, dB
30
25
MA G/MSG
common emitter
20
15
MA G/MSG
common base
10
5
MA G/MSG
common collector
0
1
Monolithic amplifiers are not easily made unilateral, so U of
only historical relevance to IC design.
U is usually valuable for fmax extrapolation
10
Frequency, GHz
100
Excess Collector Capacitance, Fmax, and Device Utility
Ccbx
40
U: all 3
35
Rbe
Ccbi
Cbe
Rc
S21
S12

Y21
Y12

30
C
gm Vbe
Gains, dB
B
Rbb
MSGCE 
1

ωCcb  Rex  kT

qI
c

25
MA G/MSG
common emitter
20
15
MA G/MSG
common base
10
Rex
E
5
f max 
MA G/MSG
common collector
0
1
10
Frequency, GHz
100
T hepartit ioning bet ween Ccbi and Ccbx will be discussed later.
Ccbx has no effect upon f max or U.
Ccbx has a large impactupon common- emitterMSG,
hencehas large impacton usable gain in mm - wave circuit s.
Ccbx has a large impactupon digit al logic speed.
high fmax does not mean low Ccb or fast logic
ft
8Rbb Ccbi
What do we need: ft , fmax , or … ?
Tuned ICs (MIMICs, RF):
fmax sets gain,
& max frequency, not ft.
…low ft/fmax ratio makes
tuning design hard (high Q)
high Ccbx reduces MSG
Lumped analog circuits
need high & comparable ft
and fmax.
Ccb/Ic has major impact
upon bandwidth
Distributed Amplifiers
in principle, fmax-limited,
ft not relevant….
(low ft makes design hard)
digital ICs will be discussed in detail later
transistor
electrical
parameters
HBT DC Characteristics
HBT transit times
Emitter Resistance
Dino Mensa
Emitterresistance: one limitingfactorin scaling for speed
high speed devices: high J  low Ccb I c 
but high J  excessiveI E Rex  voltagedrop
evidence of edge depletion or damage
Rex ?
c
LE WE  W 
1
 LE  c WE  W 
Rex
Low resistanceobtainedwith Inx Ga 1-x As emittercaps with high In fraction.
Processcontrolfor removalof surface oxidesis important.
T i/Pt/Aucontactsstill best at present
Current Gain: surface conduction, not recombination
Surface Conduction:
InGaAs has low surface recombination velocity.
InGaAs has surface pinning near conduction band.
→ weak surface inversion layer on base, surface conduction to base contact
Problem aggravated by InP emitter, as this also pins near conduction band
I b I surface I bulk
 

 Ic
Ic
Ic
1

PE (k1qnpo )
AE (qnpo Dn / Wb )

1
 bulk
evidence of surface conduction
Dino Mensa
emitter
base
Be: InGaAs
4E19/cm3 doping
Passivation with Silicon Nitride: Ledges
Literature suggests that coating InP with Silicon Nitride produces surface states
~200 meV below conduction band edge → surface pinning → leakage
Use InGaAs/InAlAs grades (sketches below) to form ledges: surface pinning for
SiN-coated InAlAs is ~400 meV below band edge.
Not understood; some processes with SiN on InGaAs or InP still have low leakage.
grade
SiN
N+
N-
P+
metal
base parameters
Base Transit Time
Dino Mensa
Assumes:
DN  40 cm2 / V  sec
vexit  3 107 cm/s

t b  Wb Lg / Dn  L2g / Dn  Lg / vsat 1  e
Wb / Lg

where Lg is thegrading length:
Lg  Wb kT / Eg 
Drift - diffusion modelcorrectif
τb  t m  Dn m* / kT  35 fs
Base Transit Time: Grading Approaches
Dino Mensa
Miguel Urteaga
Mattias Dahlström
Compositional grading: strained graded InGaAs base
Base-emitter junction with InAlAs/InGaAs CSL
UCSB data showed limited improvement with > 50 meV grading
Findings similar to that of Ritter Group /Technion
Stain effects on bandgap must be included in grade design
52 meV potentialdrop : In0.455Ga 0.545As  In0.53Ga 0.47As (strained)
Doping grading: carbon graded from ~8 to 5E19
Abrupt (InP-InGaAs) base-emitter junction
Analyses by Ishibashi, others, suggests that abrupt launcher has
minimal effect on transit time in > 30 nm bases
Doping grading is only effective for degenerate base doping; otherwise
large doping change induces only small field but
requires large sacrifice in base sheet resistance
UCSB has used both approaches; neither appears to be conclusively superior .
Limits on Base Doping
Loss of current gain due to Auger Recombination
At high dopings,bulk recombination dominatedby Auger
t Auger  1 N
2
A
Since t base  1 T
2
B
   1 ( N ATB )  1/
2
2
sheet
For doping 10 / cm , we observemorerapid decrease
20
of  than1/
2
sheet
3
.
Causes : effect of high carbon concentration on strain ?
verylow acceptorionization?
base-collector RC
parasitics
Base-Collector Distributed Model: exact
This "mesh model" can be entered into a microwave circuit simulator (e.g. Agilent ADS)
to predict fmax , etc.
After Pulfrey / Vaidyanathan
Components of Rbb and Ccb
Miguel Urteaga
Rhoriz  sWbc / 2LE
Ccb,e  LeWe / Tc
Rx  Rhoriz  Rvert Rcont  Rcont !
Pulfrey / Vaidyanathan fmax model
Note that theexternalcapacitance
Ccb,ext is charged througha relatively
low resistance, less than Rvert .
Ccb,ext Rcont Rvert   Ccb,ext Rvert


1
Tc  contact
...theassociatedcharging time
is relativelysmall
Ccb,ext has moderateeffect upon f max ,
but big impactupon
digital and analogspeed
collector spacecharge effects
Scaling Laws, Collector Current Density, Ccb charging time
InGaAs base
GaAsSb base
Collector Depletion Layer Collapse
Vcb,min    (qNd )(Tc2 / 2 )
0 mA/m2
0 mA/m2
Collector Field Collapse (Kirk Effect)
Vcb    ( J / vsat  qNd )(Tc2 / 2 )
10
mA/m2
10 mA/m2
 J max  2veff (Vcb  Vcb,min  2 ) / Tc2
NotethatVbe   , hence(Vcb   )  Vce
Ccb VLOGIC / I C  Acollector Tc VLOGIC
 Acollector
VLOGIC

IC  
VCE  VCE ,min   Aemitter
 TC


 2veff




Collector capacitance charging time scales linearly with collector thickness if J = Jmax
Kirk effect in DHBTs
500
0.6 V
cb
0.0 V
 2vsat (Vce  Vce,min ) / Tc2
cb
-0.2 V
300
cb
f , -0.3 V
t
200
J max  2vsat (Vcb  Vcb,min  2 ) / Tc2
0.2 V
cb
t
Kirk - effect thresholdincreases
with increasedVce
400
f (GHz)
Decreasein ft and f max at high J
100
0
2
cb
4
6
8
2
J (mA/um )
10
12
e
I
b step
= 180 uA
40
35
12
30
10
25
Peak f , f
8
t
max
20
6
15
4
10
2
5
0
0
0
0.5
1
1.5
V
ce
(V)
2
2.5
c
where theeffectivecollector
currentflux area is
Aeffective  LE WE  2TC 
cb
I (mA)
dVce
T
 Rspacecharge 
dIc
2vsat Aeffective
V =0V
2
2
c
2
14
Je (mA/m )
Increasein Vce, sat with increasedJ
A = 0.6 x 4.3 m
jbe
16
T. Ishibashi
Collector Transit Time
From elementaryelectrostatics (refer tosketch)
tc 
(1  x / Tc )
Tc
dx

0 v( x)
2veff
TC
t c is moresensitiveto velocitynear base.
Fortuitous, as initialvelocityis high,
thendecreases due to  - L scattering.
From best fit toRF data,or from Kirk current density vs. collectorvoltage:
InGaAs : veff  3.5 107 cm/s for ~ 200 nm layers.
InP :  3.5 107 cm/s for ~ 100- 200 nm layers
T. Ishibashi
Current-induced Collector Velocity Overshoot
2.5
1.5
ec
tau , ps
2
J=0
1
300 Å InGaAs base
2000 Å InP collector
280 GHz peak ft
0.5
0
0
0.5
1
1.5
2
2.5
2
inverse current density, 1/J, m /mA
3
3.5
Increasedcurrent reduces  - L scattering,
increasesv ( x ) in early part of collector
 reduced collectortransit time
(1  x / Tc )
dx is not exactlyproportion
al to I c
v( x)
0
TC
Qbase  I c  
J= 8
mA/um2
correctdefinitionof collectortransit time is
Q
Q
t c  base nott c  base
I c
Ic
Nakajima, H. "A generalized expression for collector transit time of HBTs
taking account of electron velocity modulation," Japanese Journal of
Applied Physics, vo. 36, Feb. 1997, pp. 667-668
CAUTION : observed nonlineart ec variation is also in part due to modulation in emitter ideality factor wit h bias current (1/g m often does not vary as Rex  nkT / qI E ), and due to variation of C je with bias.
Transit time Modulation Causes Ccb Modulation
Qbase  constant Qbase
holes
Tc
electrons
Q
Ccb   base holes
Vcb
 0 qn( x ) A1  x / Tc dx  Vbc A / Tc  f ( I c ,Vcb )
t f
Qbase holes
Ccb
tf 


I c
I c
Vcb
500
cb
400
0.0 V
cb
-0.2 V
300
2
cb
f , -0.3 V
t
200

0.2 V
cb
t
L
Kirk Effect :
t f Vcb  0  Ccb I c  0
0.6 V
f (GHz)
2
1
cb
0
eV
eV
h o les
Camnitz and Moll, Betser & Ritter, D. Root
CollectorVelocity Modulation:
t f Vcb  0  Ccb I c  0
1
I b , ΔQb a se
100
-1
0
2
4
6
8
2
J (mA/um )
10
12
0
-1
e
-2
200
nm
300
400
-2
-0.2 V
0
7
C /A (fF/m )
100
2
0
8
- weak effect in InP DHBTs
e
- strongeffect in InGaAsSHBTs
200
nm
300
400
6
5
cb
Increasein τ c with Vcb  reduced Ccb
100
4
0.0 V
Increasein Ccb is due to both
0.2 V
3
V = 0.6 V
cb
2
0
2.5
5
7.5
J (mA/m2)
e
10
12.5
- base pushoutinto collector
- and modulationof τb by Vcb
M. Urteaga
Transit time Modulation → Negative Resistance → Infinite Gain
positiveG12
 negativeconductance
negativecapacitance
Ccb ,canc   I c t f / Vcb 
negativeresistance
R  2(t c / 3Ccb ,canc )
negativeG22
 negativeconductance
equivalent
circuit
model
Transistor Hybrid-Pi equivalent circuit model
Ccbx
B
Rbb
Rbe
gm0  qIE / nkT
 j (t b t c )
g m  g m0 e
Cbe  C je  gm (t b  t c )
Ccbi
Rc
Cbe
gm Vbe
Rex
E
C
Comments regarding the Hybrid-Pi model
T hecommon- base (T )modeldirectlymodels
frequency- dependenttransport
T hehybrid- pi model results froma fit t otheT to first order in  .
T hecapacit ance Cbe ,diff models theeffectof (t b  t c )
on input impedance
T he g m generatornevert heless also requires
an associat ed~ (0.2t b  t c ) delay (import antin fast IC design)
Rbb Ccbi and Ccbx representfit s
to thedistributed RC base - collectornetwork
thermal
considerations
Fast DHBTs: high current density  high temperature
Caused by
Low K
of InGaAs
Ian Harrison
U. Nottingham
Max Trise in
Collector
40
Temperature Rise (K)
35
center
Edge
30
25
20
15
10
5
SC
ES
C
B
E
E Metal
0
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Distance from substrate (m)
• Thermal conductivity of InGaAs ~ 5 W/mK
• Thermal conductivity of InP ~ 68 W/mK
• Average Tj (Base-Emitter) =26.20°C
• Measured Tj=26°C—good agreement
Conclusions…
Minimize InGaAs thickness in subcollector
Use narrow emitter stripes
Thermal conductivity of common materials
Mattias Dahlström
100
at 300 K
Si (168)
 (W/Km)
80 InP
60
GaAs
40
InAs
20
InGaP
InAlAs
InGaAs
SiN
SiO polyimid
0
Material
Ternaries lattice matched to InP
Mattias Dahlström
Where is the heat generated, how is it removed ?
0.5
0
-0.5
InGaAs
E
E (eV)
InGaAs
-1
c
-1.5
-2
InGaAlAs
InP
InP
Base
E
Emitter
InGaAs
v
-2.5
Collector
-3
50
100
150
200
Position (A)
250
300
350
JE x VCE=6 x 1.5 V=9 mW/m2 In the intrinsic collector
Main heat transport is through the subcollector to the substrate
Up to 30 % heat transport up through the emitter contact
For small thermal resistance: InP collector, InP subcollector, only thin InGaAs in subcollector, InP emitter,
narrow emitter junction for radial heat flow
Mattias Dahlström
Experimental Measurement of Temperature Rise
Vbe fixed I
c
0.0022
dVbe dT dP

VCE
dT dP dVCE
0.002
0.0018
 (V/K)
    JA I CVCE
0.0016
0.0014
0.0012
dVbe
  JA 
dVCE

fixed I c
1
0.001
I C  
0.0008
Thermoelectric feedback coefficient from Liu et al.
0.0006
0.001
0.01
0.1
2
J (mA/m )
1
10
e
0.014
0.012
Meta run 11 (BCB)
E05B05
c
I (A)
0.01
0.008
Ic
Vce  1.5V
Vce  1.3V
0.006
No thermal instability as long as slope<∞
each VBE gives a unique IC
0.004
0.002
0.91
Temperature rise
calculated by measuring IC,
VCE and VBE
0.92
0.93
0.94
0.95
V (V)
be
0.96
VBE
0.97
0.98
W. Liu: “Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors”
, IEEE Transactions on Electron Devices, Vol 42 No6, June 1995
W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities of InP-Based
Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 43 No3,
March 1996
Example of Thermal Data
Zach Griffith
Current Hogging and Emitter Finger Ballasting
25
120
c
I , mA
80
b
15
10
5
60
0
c
I , mA
I step = 300 A
20
100
Yun Wei
0
40
1
2
3
4
V , Volts
5
6
ce
I step = 380 A
20
b
0
0
1
2
3
V , Volts
4
5
ce
Assume initial temperature differenceT between 2 fingers
dVbe
  at constantI c
dT
dV
1
T  Vbe  be T  I C 
Vbe
dT
Rex  Rballast  kT / qIE
 P  VCEI C  T   JAP
Unstableunless
K thermalstability 
dVbe
VCE JA
1
dT Rex  Rballast  kT / qIE
W. Liu, H-F Chau, E. Beam III, "Thermal properties and thermal
instabilities of InP-based heterojunction bipolar transistors", IEEE
Transactions on Electron Devices, vol.43, (no.3), IEEE, March
1996. p.388-95.
Thermal runaway within a finger
emitter
With long emitter finger, current-crowding can occur within finger
• Long finger: temperature can vary along length of emitter finger
loss of strong thermal coupling
•Temperature gradients along finger results in nonuniform current distribution
center of stripe gets hotter  carries more current  gets hotter  …
Premature Kirk-effect-induced collapse in ft.
Yun Wei
Measurement of Current hogging in multi-finger DHBT
0.05
0.04
0.03
0.02
0.01
0
0
0.5
1
1.5
W. Liu, H-F Chau, E. Beam III, "Thermal properties and thermal instabilities of InP-based heterojunction bipolar transistors", IEEE Transactions on Electron Devices, vol.43,
(no.3), IEEE, March 1996. p.388-95.
2
mesa transistor
results
Zach Griffith
InP Mesa DHBTs; 600 nm Emitter Scaling Generation
1.7 m base-collector mesa
1.3 m base-collector mesa
Zach Griffith
DC, RF performance—150 nm collector, 47 nm transition
A = 0.6 x 4.3 m
V =0V
jbe
cb
7
I
= 85 uA
b step
6
400
f
300
t
200
21
20
V = 0.6 V
cb
1
15
A
jbe
2
3
4
5
J (mA/um2)
6
e
2
= 0.6 x 4.3 um
c
2
4
8
3
2
4
max
10
0
0.5
10
10
Frequency (Hz)
11
10
Emitter contact (from RF extraction), Rcont = 10.1 m2
Base (from TLM) : Rsheet = 564 /sq, Rcont = 9.6 m2
1.5
ce
2
2.5
0
(V)
2
0.01 Ajbe = 0.6 x 4.3 m
12
Average   36, VBR,CEO = 5.1 V (Ic = 50 A)
1
V
= 505 GHz
10
-4
10
-6
10
-8
I
c
n = 1.17
c
9
10
12
max
I
c
b
b
f = 391 GHz, f
0
t
0
Ccb/Ic ~0.5 ps/V
cb
I , I (A)
e
t
Peak f , f
ce
J = 5.17 mA/um , V = 0.6 V
5
5
1
I = 13.2 mA, V = 1.54 V
10
16
c
H
max
10
I (mA)
25
GHz
U
30
Gains (dB)
f
500
2
35
Je (mA/m )
2
n = 1.38
b
-10
Collector (from TLM) : Rsheet = 11.9 /sq, Rcont = 5.4 m210-12
V
V
0
0.2
CB
CB
= 0.0 V (dashed)
0.4
0.6
V (V)
be
= 0.3 V (solid)
0.8
1
Zach Griffith
DC, RF performance—120 nm collector, 42 nm transition
35
h
21
20
VCB = 0.0 V (dashed)
0.01
10
-4
10
-6
V
= 0.3 V (solid)
c
n = 1.12
c
b
15
CB
I
c
I , I (A)
Gains (dB)
25
Gummel characteristics
Average   40, VBR,CEO = 3.9 V.
Emitter contact Rcont < 10 m2
Base: Rsheet = 610 /sq, Rcont = 4.6 m2
Collector: Rsheet = 12.1 /sq, Rcont = 8.4 m2
U
30
30 nm base
10
f = 450 GHz, f
t
max
10
= 490 GHz
I
-8
b
n = 1.41
5
b
-10
10
0
9
10
10
1.5ps/V
10
V
8
-12
12
10
10
0
1.0 ps/V
cb
= -0.3 V
0.8 ps/V
20
-0.2 V
0.6 ps/V
15
cb
6
25
C (fF)
0.0 V
0.4 ps/V
e
C /A (fF/m2)
11
10
10
Frequency (Hz)
0.2 V
10
cb
4
V
2
cb
= 0.6 V
C /I =0.2 ps/V
cb c
Ajbe = 0.6 x 4.3 m
2
A = 1.3 x 6.5 m2
jbc
0
0
2.5
5
5
7.5
2
J (mA/m )
e
10
0
12.5
0.25 0.5 0.75
V (V)
be
1
Zach Griffith
DC, RF performance—100 nm collector, 42 nm transition
35
100 nm collector, 30 nm base
H
30
2
jbe
= 0.6 x 4.3 um
c
ce
2
e
t
0
9
10
max
40
12.5
Peak f , f
t
10.0
30
max
7.5
20
10
0
0
= 415 GHz
10
50
0.0
cb
f = 491 GHz, f
= 180 uA
2.5
J = 10.3 mA/um , V = 0.4 V
5
b step
5.0
I = 27.8 mA, V = 1.37 V
10
I
15.0
e
15
cb
0.5
1
1.5
2
2.5
V (V)
ce
11
10
10
Frequency (Hz)
2
0.01 Ajbe = 0.6 x 4.3 m
12
10
I
-4
10
I , I (A)
Summary of device parameters—
n = 1.12
c
b
10
n = 1.44
b
Emitter contact (from RF extraction), Rcont  7.8
m2
Base (from TLM) : Rsheet = 629 /sq, Rcont = 6.2
m2
Collector (from TLM) : Rsheet = 12.9 /sq, Rcont = 4.0
I
-6
c
Average   40, VBR, CEO = 3.1 V (Ic = 50 A)
c
-8
b
10
-10
10
V
CB
V
-12
m210
CB
0
0.2
= 0.3 V (dashed)
0.4
0.6
V (V)
be
= 0.0 V (solid)
0.8
1
c
20
A
V =0V
I (mA)
J (mA/m2)
U
MSG/MAG
2
17.5
21
25
Gains (dB)
A = 0.6 x 4.3 m
jbe
20.0
Summary of HBT performance: April 2005
200 GHz 300 GHz 400 GHz
700

500 GHz
ft f max
popularmetrics :
Pohang
SHBT
250 nm
( ft  f max ) / 2
ft f max
600
UCSB T.S
SHBT (?)
NGST
DHBT
150 nm
UCSB
210 nm
400
150 nm
IBM
SiGe
300
HRL
DBHT
200
better metrics :
UCSB
120 nm
120 nm
poweramplifiers :
P AE,
UCSB
100 nm
associatedgain,
mW/m
RSC
DHBT
150 nm
SFU
DHBT
200 nm
f
max
(GHz)
500
(1 ft  1 f max ) 1
NTT
DHBT UCSB
150 nm 150 nm
low noiseamplifiers :
65 nm
150 nm
IBM
SiGe
100 nm
F min ,
UIUC
75 nm
SHBT
associatedgain,
100 nm
associatedDC power
digital:
100
f clock , hence
(Ccb V / I c ),
Updated April 12, 2005
0
0
100
200
300
400
ft (GHz)
500
600
700
( Rex I c / V ),
( Rbb I c / V ),
( τb  τc )
Comparison with InP HEMTs
350
600
400
450
500 GHz
fT × fmax
HBTs have better breakdown than HEMTs
→ use HBTs for power amplifiers
HEMTs have better noise than HBTs
→ use HEMTs for LNAs
400
300
1.0
200
200
100
100
200
300
Keisuke Shinohara
CRL Japan
(Now at Rockwell Scientific)
300
250
400
fT (GHz)
Gate
( Ti / Pt / Au )
500
600
Drain current (A/mm)
fmax (GHz)
500
Lg = 30 nm
Vgs = 0 ~ -0.8 V in 0.2 V step
0.8
0.6
527
509
475
419
0.4
0.2
0.0
0.0
Lg = 30 nm
534
fT value
338
532
526
512
485
511
498
440
475
233 387
435
463
374
434
281
332
381
305
228
374
313
190 223
111
142 224
32 67 85
0.2
0.4
0.6
0.8
Drain-source voltage (V)
transistor
scaling theory
HBT scaling: layer thicknesses
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,
WE
WEB
LE
emitter
base
x
reduce Tb by 2:1
 tb improved 2:1
reduce Tc by 2:1
 tc improved 2:1
note that Ccb has been doubled
..we had wanted it 2:1 smaller
base
collector
WC
WBC
t b  Tb2 / 2Dn
t b  Tc / 2vsat
AssumeWC ~ WE
t 's
HBT scaling: lithographic dimensions
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,
Rbb  Rgap  Rspread  Rcontact
Base Resistance Rbb must remain constant
 Le must remain ~ constant
 Rcontact
  sheet  c ,vertical 2 LE
Ccb/Area has been doubled
..we had wanted it 2:1 smaller
…must make area=LeWe 4:1 smaller
 must make We & Wc 4:1 smaller
WE
WEB
LE
emitter
base
x
reduce collector width 4:1
reduce emitter width 4:1
keep emitter length constant
t 's
base
collector
WC
WBC
AssumeWC ~ WE
HBT scaling: emitter resistivity, current density
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,
Emitter Resistance Rex must remain constant
but emitter area=LeWe is 4:1 smaller
resistance per unit area must be 4:1 smaller
AssumeWC ~ WE
Collector current must remain constant
but emitter area=LeWe is 4:1 smaller
and collector area=LcWc is 4:1 smaller
current density must be 4:1 larger
WE
WEB
LE
emitter
base
increase current density 4:1
reduce emitter resistivity 4:1
x
t 's
base
collector
WC
WBC
Bipolar Transistor Scaling Laws
WE
WEB
LE
Scaling Laws:
design changes required
to double transistor bandwidth
emitter
base
x
base
collector
WC
key device parameter
required change
collector depletion layer thickness
decrease 2:1
base thickness
decrease 1.414:1
emitter junction width
decrease 4:1
collector junction width
decrease 4:1
emitter resistance per unit emitter area
decrease 4:1
current density
increase 4:1
base contact resistivity
(if contacts lie above collector junction)
decrease ~4:1
base contact resistivity
(if contacts do not lie above collector junction)
unchanged
WBC
digital / mixed
signal IC design
and relationship
to transistor
We design HBTs for fast logic, not for high ft & fmax
Gat e Delay Determinedby :
Deplet on
i capacit ance charging
t hrought helogic swing
 VLOGIC 

Ccb  Cbe ,depletion
 IC 
Deplet on
i capacit ance charging
t hrought hebase resist ance
Rbb Ccbi  Cbe ,depletion
Supplyingbase  collect or
st oredcharge
t hrought hebase resist ance
 IC 

Rbb t b  t c 
 VLOGIC 
T helogic swing must be at least
 kT

VLOGIC  4  
 Rex I c 
 q

out
out
in
in
clock
clock
clock
clock
(t b  t c ) t ypically 10 - 25% of totaldelay;
Delaynot wellcorrelat edwit h ft
VLOGIC
I C Ccb  Cbe ,depl  is 55% - 80% of total.
High I C / Ccb  is a key HBTdesign object ive.
J max,Kirk  2εvelectron(Vce, operating  Vce,full depletion ) / Tc2
 Acollector  TC 



 Aemitter  2velectron 
Rex must be verylow for low Vlogic at high J

CcbVLOGIC VLOGIC

IC
2VCE ,min
InP HBT Roadmaps: 40 / 80 / 160 Gb/s digital clock rate
Key scaling challenges
emitter & base contact resistivity
current density→ device heating
collector-base junction width scaling
& Yield !
key figures of merit
for logic speed
Why isn't base+collector transit time so important for logic?
Diffusion capacitance :
Q base  (t b  t c )I C
 (t b  t c )
Vout(t)
Vout
Vin
t
(t b  t c ) I C
Vbe
kT / q
...activeonly over kT / q volt ageswing.

Under Large - Signal Operat ion:
Q base  (t b  t c ) I C

t
Vin(t)
dIC
Vbe
dVbe
diffusion
+ depletion
capacitance
only depletion
capacitance
(t b  t c ) I dc
VLOGIC
VLOGIC
Large - signal diffusion capacitance
reduced by ratioof
 VLOGIC

 kT / q

, which is ~ 10 : 1

Depletion capacitances present over full voltage swing, no large-signal reduction
Scaling Laws, Collector Current Density, Ccb charging time
InGaAs base
GaAsSb base
Collector Depletion Layer Collapse
Vcb,min    (qNd )(Tc2 / 2 )
0 mA/m2
0 mA/m2
Collector Field Collapse (Kirk Effect)
Vcb    ( J / vsat  qNd )(Tc2 / 2 )
10 mA/m2
 J max  2veff (Vcb  Vcb,min  2 ) / Tc2
10 mA/m2
NotethatVbe   , hence(Vcb   )  Vce
Ccb VLOGIC / I C  Acollector Tc VLOGIC
 Acollector
VLOGIC

IC  
VCE  VCE ,min   Aemitter
 TC


 2veff




Collector capacitance charging time scales linearly with collector thickness if J = Jmax
Key HBT Scaling Limit  Emitter Resistance
RL
ECL delay not well correlated with ft or fmax
Rex
Largest delay is charging Ccb
Ccb
Vlogic
IC
Io
εAcollector Vlogic

; where J e,max  1/Tc2 .
TC
J e Aemitter
Noise margin
 Je  10 mA/m2 needed for 200 GHz clock rate
Vin
Voltage drop of emitter resistance becomes excessive
RexIc = exJe = (15 m2)  (10 mA/m2) = 150 mV
Vlogic
 considerable fraction of Vlogic  300 mV
Degrades logic noise margin
 ex  7 m2 needed for 200 GHz clock rate
Vout
2kT/q+IoRex
Vlogic=IoRL
Breakdown: Thermal failure is more significant than BVCEO
14
0.5 um X 7 um emitter
junction
2
A0.5
=0.6
x
7
m
um
base
contact
width
jbe
Ib step = 0.4 mA
High ft and f max requires high J e
10
 low - current breakdown oftennot relevant
8
6
e
2
J (mA/m )
12
Breakdown- Vbr ,ceo or Vbr ,cbo - is measured at low J e
1
Vbr ,ceo  EmaxTcollector decreases moreslowly than f clock
~6.8 V low-current
BVCEO
4
2
because Emax increases with thincollectors
0
0
1
2
3
4
5
6
7
8
V (V)
ce
12
~ 7 K  ( m)2 / mW therma
l resistance
biased without
failure (DC-IV)
J
Dissipation limitspower density
device failure
18 mW/um 2
8
design limit 10 mW/um
No RF drift
after 3-hr
ECL
burn-in
6
max
(mA/um 2)
10
2
2
P AE  J EVce  f clock
VCE
2
 Vmax  1 /  ja f clock
bias points
4
2
0
8 m emitter metal length,
~0.6 m junction width
0
1
2
3
V (V)
ce
4
5
data above Jan. 2004;
failure now @ >29 mW/um2
6
Low thermal resistance is critical.
DHBTs are superior to SHBTs.
digital IC results
Digital circuits:
towards 200 GHz
clock rate
142 GHz latch from NNIN @ UCSB, 150 GHz
ICs from UCSB/GSC/RSC
200 GHz is the next goal
underlying technology:
400-500 GHz InP transistors
Z Griffith
Static Frequency Divider: Standard Digital Benchmark
ECL Master-Slave Latch with Inverting Feedback
Forms 2:1 Frequency Divider.
Maximum clock frequency is measure
of technology speed.
Standard circuit configuration for consistent
benchmarking - no tricks.
Small inductive peaking (L/R~1.3 ps).
One clock period has 2 latch delay.
Each latch is a 2-input gate with an equivalent
fanout of 2 or 3
→ much more strenuous test
than 2:1 mux or ring oscillator
Z Griffith
Hierarchy of ECL Static Frequency Divider
ECL NAND/NOR Gate
ECL Latch: level-clocked memory element
Level Shifters
Level Shifters
Logic Gate Core
Zo
C
D
Q
Master-Slave Latch:
transition-clocked memory element
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
2:1 Static Frequency Divider
D
C
Q
Q
D
Q
C
Q
CPW has parasitic modes, coupling from poor ground plane integrity
kz
+V
0V
0V
CPW mode
0V
+V
+V
+V
-V
+V
0V
0V
Microstrip mode
0V
Substrate modes
Slot mode
ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductance
ground vias suppress microstrip mode, wafer thinning suppresses substrate modes
Microstrip has high via inductance, has mode coupling unless substrate is thin.
kz
We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs
M. Urteaga, Z. Griffith, S. Krishnan
IC design: Z. Griffith, UCSB
HBT design: RSC / UCSB / GCS
IC Process / Fabrication: GCS
Test: UCSB / RSC / Mayo
UCSB / RSC / GCS 150 GHz Static Frequency Dividers
size
m2
data
current
steering
0.5 x 3.5
current
density
Ccb/Ic
mA/m2
6.9
4.4
4.4
4.4
psec / V
0.59
0.99
0.74
0.86
Vcb
V
0.6
0
0.6
1.7
ft
GHz
301
260
301
280
fmax
GHz
358
268
358
280
units
Minimum input power (dBm)
-30
Output Power (dBm)
Output Power (dBm)
-20
-30
-40
-50
-60
-70
-40
-50
-60
-70
0.00
38.00
57.00
frequency (GHz)
76.00
74.9975
10
0
-10
-20
probe station
chuck @ 25C
-30
0
-80
19.00
clock
emitter
followers
0.5 x 5.5
-40
-80
-90
clock
current
steering
0.5 x 4.5
PDC,total = 659.8 mW
divider core without
output buffer  594.7 mW
20
-10
data
emitter
followers
0.5 x 4.5
74.9987
75.0000
75.0012
frequency (GHz)
75.0025
20
40
60 80 100 120 140 160
frequency (GHz)
Z. Griffith, M. Dahlström
UCSB 142 GHz Master-Slave Latches (Static Frequency Dividers)
Static 2:1 divider:
Standard digital
benchmark.
Master-slave latch
with inverting feedback.
Performance comparison
between digital
technologies
UCSB technology 2004:
InP mesa HBT technology
12-mask process
600 nm emitter width
142 GHz maximum clock.
-10
100 + Gb/s serial links
Target is 260 GHz clock
rate at 300 nm scaling
generation
Output Power (dBm)
Implications:
160 Gb/s fiber ICs
25o C
-20
-30
-40
-50
-60
-70
-80
-90
0.0
15.0
30.0
45.0
frequency (GHz)
60.0
75.0
Reducing Divide-by-2 Dissipation
50 Ohm
50 Ohm bus
50 Ohm
ECL with impedance-matched
50 Ohm bus:
25 Ohm load→ switch 12 mA
12 mA x 7 x 4 V = 336 mW/latch
12 mA
50 Ohm
50 Ohm bus
50 Ohm
CML with impedance-matched
50 Ohm bus:
25 Ohm load→ switch 12 mA
12 mA x 3 x 3 V = 108 mW/latch
12 mA
12 mA
100 Ohm
12 mA
50 Ohm bus
Low-Power CML
100 Ohm loaded → switch 3 mA
3 mA x 3 x 3 V = 27 mW/latch
100 Ohm
3 mA
High speed @ low power  low Cwiring , low Ccb, pad
3 mA
3 mA
Significant dissipation in the emitter-follower level-shifters
Ccb/Ic Charging Rate: ECL is much better than CML
10
CML
V
8
cb
25
= -0.3 V
20
-0.2 V
15
e
0.0 V
0.2 V
10
cb
4
V
2
cb
= 0.6 V
5
0
 TC

 2velectron
10
V
logic



5
7.5
10
2
J (mA/m )
e
V
= 300mV
8
cb
25
= -0.3 V
20
-0.2 V
0.2 V
4
10
V
2
cb
= 0.6 V
5
0
0
2.5
5
7.5
2
J (mA/m )
e
10
0
12.5
cb
15
0.0 V
C (fF)
6
e
Zo
 Acollector

 Aemitter
2.5
0
12.5
cb
ECL
0
C /A (fF/m2)
Ccb VLOGIC
VLOGIC

IC
VCE  VCE , min
cb
6
C (fF)
C /A (fF/m2)
Zo
Phase II divide by 2—Ultra low power CML divider
Simulated divider speed…
With Collector Pedestal
470 m
Ajbe = 1.0 m2, fmax = 100 GHz
Pdivider core,  31 mW
443 m
mm-wave
amplifiers
Tuned Amplifier Design for Maximum Gain
If Device is Unconditionally Stable
Simultaneously match input and
output of device
MAG 
S21
S12
K 
K 1
2

g e ne ra tor
loa d
R ge n
Vg e n
los s le s s
ma tc h in g
ne two rk
los s le s s
m a tc hin g
n e two rk
RL
K = Rollet stability factor
If transistor is unconditionally stable, circuit gain is transistor MAG
If Device is Potentially Unstable
Stabilize transistor and simultaneously
match input and output of device
MSG 
S21
Y
 21
S12
Y12
g e ne ra tor
loa d
R ge n
Vg e n
los s le s s
m a tc hin g
n e two rk
re s is tive
los s
(s ta b iliz a tio n)
If transistor is potentially unstable, circuit gain is transistor MSG
Design for maximum gain is rare;
usually one designs for maximum saturated power or for minimum noise.
Gain is then less, discussion is beyond our scope
los s le s s
ma tc h in g
ne two rk
RL
V. Paidi, Z. Griffith, M. Dahlström
Common-Base Has Highest Gain, but Layout Parasitics Matter
30
U
base plug
25
MSG/MAG, dB
base
Lb
ignores layout parasitics
20
Common emitter
15
Common base
10
Common Collector
5
0
100
10
Frequency, GHz
25
Without C , L
MSG/MAG
20
interconnect metal
Cce
emitter
base
N- collector
N+ subcollector
semi-insulating InP
ce
With C
15
10
Cce
collector
b
With C
5
ce
and L
b
0
10
100
Frequency, GHz
ce
mm-wave IC
results
M. Urteaga
Deep Submicron Bipolar Transistors for 140-220 GHz Amplification
raw 0.3 m transistor: high power gain @ 200 GHz
Transistor Gains, dB
40
30
unbounded U
U
U
20
MSG/MAG
10
H
21
0
10
100
1000
Frequency, GHz
8
6
S21, dB
4
2
0
-2
-4
140
1-transistor amplifier:
6.3dB @ 175 GHz
150
160
170
180
190
200
210
220
Frequency, GHz
gain, dB
10
0
-10
-20
-30
140
3-transistor amplifier:
8 dB @ 195 GHz
150
160
170
180
190
Frequency (GHz)
200
210
220
Miguel Urteaga
175 GHz Single-Stage Amplifier
10
S21
S11
S22
50
0.2pF
5
80
1.2ps
30
0.2ps
80
1.2ps
50
30
1.2ps
0
50

0.6ps
dB
IN
OUT
-5
-10
-15
-20
140
150
160
170
180
190
200
Freq. (GHz)
6.3 dB gain at 175 GHz
210
220
172 GHz Common-Base Power Amplifier
Input Matching Network
V. Paidi, Z. Griffith, M. Dahlström
Output Loadline
Match
Vin
8.3 dBm saturated output power
4.5-dB associated power gain at 172 GHz
DC bias: Ic=47 mA, Vcb=2.1V.
transistor fmax was 300 GHz
15
S
6 dB gain
22
5
S
0
22
S
11
21
11
21
-5
-10
140
150
160
170
Frequency, GHz
180
RL
5
4
10
Gain
3
5
Output Power
2
0
-10
190
-15
1
PAE
-5
0
-10
-5
0
Input Power, dBm
2 fingers x 0.8 um x 12 um, ~250 GHz ft, 300 GHz fmax , Vbr ~ 7V, ~ 3 mA/um2 current density
5
PAE (%)
Gain, dB, Output Power, dBm
10
S ,S ,S , dB
Vout
176 GHz Two-Stage Amplifier
V. Paidi, Z. Griffith, M. Dahlström
7-dB gain at 176 GHz
8.1 dBm output power, 6.3 dB power gain at 176 GHz
9.1 dBm saturated output power at 176 GHz
transistor fmax was 300 GHz
V
eb,bias
 at f
0
Output
Loadline
Matching
Network
Input
Matching
Network
Vin
Output
Loadline
Matching
Network
Input
Matching
Network
50 Ohms
Vout
RL
50 Ohms
 at f
0
10
5
15
4
10
cb,bias
6
3
4
2
2
1
21
22
PAE
5
S
22
11
Gain
S
0
21
8
S , S , S dB
Output Power
PAE (%)
Gain, dB, Output Power , dBm
V
-5
S
11
0
0
-6
-4
-2
0
2
4
Input Power, dBm
6
8
10
-10
140
150
160
170
180
Frequency, GHz
190
200
measurement
issues
140-220 & 220-330 GHz On-Wafer Network Analysis
• HP8510C VNA,
Oleson Microwave Lab mm-wave
Extenders
• coplanar wafer probes made by:
GGB Industries, Cascade Microtech
•connection via short length of
waveguide
• Internal bias Tee’s in probes for
biasing active devices
• 75-110 GHz set-up is similar
• DC-50 GHz set is standard coaxbased system: SNR ok only to ~30 GHz
GGB Wafer Probes
330 GHz available with bias Tees
High Frequency HBT Gain Measurements : Standard Pads
Measuring wideband transistors is very hard ! Much harder than measuring amplifiers.
Determining fmax in particular is extremely difficult once it exceeds 400 GHz
Standard "short pads"
must strip pad capacitance
must strip pad inductance--or ft will be too high !
cal bad above ~25 GHz due to substrate coupling
make pads small, or lift them off the InP !
cal bad above ~25 GHz due to probe coupling
use small probe pitch, use shielded (infinity) probes
35
35
21
25
Gains (dB)
25
Gains (dB)
U
30
h
30
20
2
15
A
10
I = 20.6 mA, V = 1.53 V
jbe
= 0.6 x 4.3 um
c
ce
2
J = 8.0 mA/um , V = 0.6 V
e
5
t
max
9
10
A
10
I = 20.6 mA, V = 1.53 V
10
10
Frequency (Hz)
jbe
= 0.6 x 4.3 um
c
ce
2
J = 8.0 mA/um , V = 0.6 V
e
cb
f = 450 GHz, f
= 490 GHz
t
max
= 490 GHz k
0
0
10
2
15
5
cb
f = 450 GHz, f
MAG/MSG
20
11
10
12
9
10
10
10
10
Frequency (Hz)
11
10
12
High Frequency HBT Measurements : On-Wafer LRL
Extended Reference planes
transistors placed at center of long on-wafer line
LRL standards placed on wafer
large probe separation → probe coupling reduced
still should use the best-shielded probes available
Problem: substrate mode coupling
method will FAIL if lines couple to substrate modes
→ method works very poorly with CPW lines
need on wafer thin-film microstrip lines
CPW
CPW has parasitic modes, coupling from poor ground plane integrity
kz
+V
0V
0V
CPW mode
0V
+V
+V
+V
-V
+V
0V
0V
Microstrip mode
0V
Substrate modes
Slot mode
ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductance
ground vias suppress microstrip mode, wafer thinning suppresses substrate modes
Microstrip has high via inductance, has mode coupling unless substrate is thin.
kz
We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs
M. Urteaga, Z. Griffith, S. Krishnan
advanced
fabrication
processes
Parasitic Reduction for Improved InP HBT Bandwidth
At a given scaling generation, intelligent choice of device geometry
reduces extrinsic parasitics
wide emitter contact: low resistance
narrow emitter junction: scaling (low Rbb/Ae)
P base
thick extrinsic base : low resistance
thin intrinsic base: low transit time
N-
SiO2
SiO2
N+ subcollector
wide base contacts: low resistance
narrow collector junction: low capacitance
These are planar
approximations to
radial contacts:
2  bulk  2  r 

ln

L
W


2
Rcontact  c
Lr
Rbulk 
Rtotal,min 
2  bulk
L
extrinsic
emitter
extrinsic
base
extrinsic
base
N+
subcollector

  contact 


1
.
34

ln

W

bulk 


→ greatly reduced access resistance
Much more fully developed in Si…
Yield & Scaling Problems: Liftoff, Undercut, Planarity
liftoff failure:
emitter-base
short-circuit
base contact
base
sub collector
S.I. substrate
excessive
emitter undercut
base contact
base
sub collector
S.I. substrate
planarization failure: interconnect breaks
base
sub collector
S.I. substrate
Yield quickly degrades as emitters are
scaled to submicron dimensions
Controlling Emitter Undercut: Wet-Etch Mesa Process
0.5 um metal
~0.4 um junction
InP
0.7 um
Front and
side
views
0.6 um metal
~0.4 um junction
InAlAs
Front and
side
views
Smaller emitters → lower yield. Need better fabrication process
Manufacturable Emitter Dielectric Sidewall Processes
First-Generation: UCSB and Rockwell Scientific
Miguel Urteaga
Si N
18.00
16.00
14.00
3 4
12.00
base contacts by
planarization
& etch-back
Ic (mA)
thin emitter
10.00
8.00
6.00
4.00
2.00
0.00
-2.00
0.00
0.50
1.00
1.50
2.00
2.50
Vce (V)
Urteaga, Rodwell , Pierson, Rowell , Brar, Nguyen, Nguyen: UCSB, RSC, GCS
2nd-Generation: Rockwell Scientific
Miguel Urteaga, Petra Rowell
electroplated
emitter and
base contacts
250 nm emitter
Urteaga, Rowell, Pierson, Brar: RSC
266 GHz ft , 133 GHz fmax, , Ccb/Ic=0.4 ps/V
1st-Generation Polycrystalline Extrinsic Emitter
Emitter junction area: 0.3 x 4 m
2
Self-aligned, A
=0.3 um x 4 um
E_junction
0.014
I =9.72 mA
C
25
0.012
CE
=100 uA
bstep
0.01
h
20
I
V =1.2 V
U
21
MAG/MSG
I (A)
15
0.008
C
21
(dB), K
30
U, MSG/MAG, h
D. Scott, Y. Wei
0.006
10
0.004
f
5
f =280 GHz
=148GHz
T
MAX
0.002
K
0
1
10
100
1000
0
0
0.5
Frequency (GHz)
1
V (V)
CE
Approach
Wide emitter contact for low emitter access resistance
Thick extrinsic base for low base resistance
Self-aligned refractory base contacts
Enabling Technology
Low-resistance polycrystalline InAs
In-band Fermi-level pinning eliminates barriers
Challenges
Very complex process
Hydrogen passivation
Resistance of Refractory contacts
1.5
2nd-Generation Epitaxial Extrinsic Emitter
C. Kadow
Wsw
Wb,cont
We,cont
We
Web
emitter contact
InP anti-oxidation layer
InAlAs current-block layer
base contact
regrown emitter
InGaAs extrinsic base
etch stop layer
InGaAs intrinsic base
BC grade
collector
Wunder
WP
Tp
Tc
pedestal
N+ sub collector
extrinsic base: 150 /square
40
I
b, step
S.I. InP substrate
= 2 mA
10
-1
10
-2
10
-3
10
-4
10
-5
0.20
10
-6
0.00
10
-7
1.00
0.80
offset
= 0.0 V
10
0
0
0.5
1
1.5
2
V [V]
ce
2.5
3
2
0.40
I
B
c
b
20
I , I [A]
0.60
c
I [mA]
c
J [mA/um ]
30
V
WE = 1.0 µm
I
C
0
Max(  ) = 7.0
0.5
1
V
be
[V]
1.5
Y. Dong
1st-Generation Collector Pedestal Implant
Implant
N+ Pedestal Formed
HBT with pedestal
HBT without pedestal
10
2
20 mW/m
device failure
N+
PN+
S.I.
S.I.
6
e
N+
2
P-
J (mA/m )
8
HBT regrowth
Junction Fabrication
4
A = 0.4 x 7 m
2
je
2
I step = 500 A
b
0
0
1
2
V
P-
N+
P-
N+
N+
S.I.
S.I.
N+
ce
3
(V)
4
5
6
Good DC characteristics
5.4 V breakdown with a 90 nm thick collector
35
AE=0.7 x 8 um
2
2.1um pedestal
CCB (fF)
30
25
1.2um pedestal
20
15
Reduced extrinsic Ccb
1.0 um pedestal
0
1
2
3
4
5
6
7
8
2
Reduced thermal resistance
JE (mA / um )
~2:1 reduction in collector base capacitance
Pedestal: Projected Performance @ 300 nm
 c ,emitter  Rex AE  6  - m2
Web
 c ,base  10  - m 2
300 nm
J e  15 mA/m 2
We
0.3 ps wiringdelay on collectorbus
ft  530GHz
f max  770GHz
Ccb / I c  0.15 ps/V
Vbr ,ceo  4 V
Wb,cont
emitter contact
InGaAs base 30nm
f clock (divider)  275GHz
50 nm
300 nm
emitter
base contact
BC grade
collector
Tp
200nm
WP
Tc
Wunder
500nm
pedestal
100nm
N+ sub collector
S.I. InP substrate
100nm
RGE+Pedestal: Projected Performance @ 250 nm
Wsw
50 nm
20 nm,2  1019 / cm3 intrinsicbase
100 nm,1020 / cm3 extrinsicbase (145/square)
We,cont
500
nm
We nm
250
InP anti-oxidation layer
InAlAs current-block layer
Wb,cont
300
nm
Web
emitter contact
InGaAs extrinsic base
etch stop layer
regrown emitter
InGaAs intrinsic base
BC grade
base contact
100nm
collector
Tp
300nm
Wunder
100nm
WP
450nm
Tc
pedestal
N+ sub collector
S.I. InP substrate
 c ,emitter  6  - m 2
 Rex AE ~ 3  - m
 c ,base  10  - m
J e  17 mA/m
2
2
2
0.3 ps wiring delay on collect orbus
f clock (divider)  330 GHz
ft  650 GHz
f max  900 GHz
Ccb / I c  0.17 ps/V
Vbr ,ceo  4 V
Indium Phosphide HBTs
InP HBT now: at 500 nm scaling generation
455 GHz ft & 485 GHz fmax
150 GHz static dividers & 180 GHz amplifiers demonstrated
200 GHz digital latches & 300 GHz amplifiers are feasible
InP HBT: future, at 125 nm scaling generation
2:1 increase in bandwidth (?)
~1 THz ft & fmax , 400 GHz digital latches & 600 GHz amplifiers ???
demands 4:1 better Ohmic contacts
demands 4:1 increased current density.
Applications:
160+ Gb/s fiber ICs,
300 GHz MIMICs for communications, radar, & imaging
GHz ADCs / DACs / DDFS / etc.
& applications unforeseen & unanticipated
End