Transcript Microprocessor Design ° Datapath • Series of components being accessed. • Including instruction memory, program counter, register file, ALU and data memory. • Critical path.

Microprocessor Design
° Datapath
• Series of components being accessed.
• Including instruction memory, program
counter, register file, ALU and data memory.
• Critical path is a complete datapath to
execute an instruction.
° Control
• Some components needs to select one out
of multiple inputs using MUX.
• Storage elements needs condition to write
data onto them.
• Control determines these conditions
CS 61C discussion 11 (1)
Jaein Jeong 2002
Instruction Execution Steps: (ADD,SUB,ORI)
° Let us identify the instruction execution steps in single
cycle processor.
° Instruction Fetch
• Read instruction memory at PC and increment PC by 4.
° Instruction Decode/Register Read
• Read register file using the fields in the instruction
° Execution
• Do the ALU operation
° Memory
• Load data from the memory or store data into the memory
° Write Back
• Write any data back to the register file if we have anything to write
CS 61C discussion 11 (2)
Jaein Jeong 2002
Instruction Execution Steps: (ADD,SUB,ORI)
° ADD, SUB, OR
• IF: Load instruction and increment PC by 4
• ID: Read two regs (ADD/SUB)
Read one reg and zero extend immediate (ORI)
• EX: Do arithmetic in ALU
• Mem: Do nothing
• WB: Write the result of ALU into reg file.
° BRANCH (beq):
• IF: Load instruction
• ID: Read two registers (rs, rt)
• EX: Calculate the difference of rs and rt in ALU
If ALUout = 0 PC <- PC + 4 + (signext(imm)||00)
ALUout != 0 PC <- PC + 4
• Mem: Do nothing
• WB: Do nothing
CS 61C discussion 11 (3)
Jaein Jeong 2002
Instruction Execution Steps: LOAD/STORE
° LOAD Word
• IF: Load instruction and increment PC by 4
• ID: Read one reg (rs) and sign extend immediate
• EX: Calculate memory address in ALU
• Mem: Read a word from memory with the address
• WB: Write the result of ALU into reg file (rt)
° STORE Word
• IF: Load instruction and increment PC by 4
• ID: Read one reg (rs) and sign extend immediate
• EX: Calculate memory address in ALU
• Mem: Write register rt into the memory
• WB: Do nothing
CS 61C discussion 11 (4)
Jaein Jeong 2002
Instruction Execution Steps: branch
° BRANCH (beq):
• IF: Load instruction
• ID: Read two registers (rs, rt)
• EX: Calculate the difference of rs and rt in ALU
If ALUout = 0 PC <- PC + 4 + (signext(imm)||00)
ALUout != 0 PC <- PC + 4
• Mem: Do nothing
• WB: Do nothing
CS 61C discussion 11 (5)
Jaein Jeong 2002
Putting it All Together:A Single Cycle Datapath
Instruction<31:0>
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Rt Rd Imm16
RegDst
ALUctr MemWr MemtoReg
Equal
Rt
Rd
1 0
Rs Rt
RegWr 5 5 5
busA
Rw
Ra
Rb
=
busW
32
32 32-bit
0
32
32
Registers busB
0
32
Clk
32
WrEn Adr 1
1 Data In
Data
imm16
32
Clk
16
Clk Memory
nPC_sel
imm16
Mux
ALU
Extender
PC Ext
Adder
Mux
PC
Mux
Adder
00
4
ExtOp ALUSrc
CS 61C discussion 11 (6)
Jaein Jeong 2002
Review: An Abstract View of the Critical Path
Critical Path (Load Operation) =
° This affects
Delay clock through PC (FFs) +
how much you
Instruction Memory’s Access Time +
can overclock
Register File’s Access Time +
your PC!
ALU to Perform a 32-bit Add +
Data Memory Access Time +
Ideal
Instruction
InstructionStable Time for Register File Write
Memory
Rd Rs Rt
5 5
5
PC
Clk
A
32
Clk
CS 61C discussion 11 (7)
Rw Ra Rb
32 32-bit 32
Registers B
ALU
Next Address
Instruction
Address
Imm
16
32
Data
32 Address
Data
In
Ideal
Data
Memory
Clk
Jaein Jeong 2002
Quiz
° Given the following information, please
calculate the cycle time of the single cycle
CPU:
• Instruction memory access time: 1 time unit
• Instruction decoding time plus register read
time: 1 time unit
• ALU operation time: 0.9 unit
• PC update time: 0.1 unit
• Data memory access time: 1 time unit
• Register file update time: 1 time unit
From Li Yin’s note
CS 61C discussion 11 (8)
Jaein Jeong 2002
Draw the data path
° Now we understand what each instruction
does, we can draw the datapath for each
instruction.
CS 61C discussion 11 (9)
Jaein Jeong 2002
Draw the data path: ADD or SUB
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Instruction<31:0>
Rt Rd Imm16
Rs Rt
5 5 5
4
00
PC
Clk
CS 61C discussion 11 (10)
Extender
PC Ext
Adder
Clk
=
ALU
Adder
Rw Ra Rb
32 32-bit
Registers
WrEnAdr
Data
Clk Memory
Jaein Jeong 2002
Draw the data path: ORI
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Instruction<31:0>
Rt Rd Imm16
Rs Rt
5 5 5
4
00
PC
Clk
CS 61C discussion 11 (11)
Extender
PC Ext
Adder
Clk
=
ALU
Adder
Rw Ra Rb
32 32-bit
Registers
WrEnAdr
Data
Clk Memory
Jaein Jeong 2002
Draw the data path: Load word
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Instruction<31:0>
Rt Rd Imm16
Rs Rt
5 5 5
4
00
PC
Clk
CS 61C discussion 11 (12)
Extender
PC Ext
Adder
Clk
=
ALU
Adder
Rw Ra Rb
32 32-bit
Registers
WrEnAdr
Data
Clk Memory
Jaein Jeong 2002
Draw the data path: Store word
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Instruction<31:0>
Rt Rd Imm16
Rs Rt
5 5 5
4
00
PC
Clk
CS 61C discussion 11 (13)
Extender
PC Ext
Adder
Clk
=
ALU
Adder
Rw Ra Rb
32 32-bit
Registers
WrEnAdr
Data
Clk Memory
Jaein Jeong 2002
Draw the data path: Branch equal
<0:15>
<11:15>
Rs
<16:20>
<21:25>
Inst
Memory
Adr
Instruction<31:0>
Rt Rd Imm16
Rs Rt
5 5 5
4
00
PC
Clk
CS 61C discussion 11 (14)
Extender
PC Ext
Adder
Clk
=
ALU
Adder
Rw Ra Rb
32 32-bit
Registers
WrEnAdr
Data
Clk Memory
Jaein Jeong 2002
Meaning of the Control Signals
° To understand control, we need to know
when each of signals is turned on.
° nPC_MUX_sel: 0  PC <– PC + 4
1  PC <– PC + 4 +
{SignExt(Im16) , 00 }
nPC_MUX_sel
Inst
Adr Memory
Adder
imm16
PC
Mux
Adder
PC Ext
CS 61C discussion 11 (15)
00
4
Clk
Jaein Jeong 2002
Meaning of the Control Signals
° MemWr: 1  write memory
° ExtOp: “zero”, “sign”
° MemtoReg: 0  ALU; 1  Mem
° ALUsrc: 0  regB;
1  immed
° RegDst: 0  “rt”; 1  “rd”
° ALUctr: “add”, “sub”, “or” ° RegWr: 1  write register
RegDst
ALUctr MemWr MemtoReg
=
32
32
WrEn Adr
Data In
Data
Clk Memory
ExtOp ALUSrc
0
Mux
ALU
CS 61C discussion 11 (16)
Mux
Extender
Equal
Rd Rt
1 0
Rs Rt
RegWr 5 5 5
busA
Rw
Ra
Rb
busW
32
32 32-bit
32
Registers busB
0
32
Clk
1
imm16
32
16
1
Jaein Jeong 2002
A Summary of the Control Signals
See
Appendix A
func 10 0000 10 0010
We Don’t Care :-)
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100
add
sub
ori
lw
sw
beq
RegDst
1
1
0
0
x
x
ALUSrc
0
0
1
1
1
0
RegWrite
1
1
1
1
0
0
MemWrite
0
0
0
0
1
0
nPCsel
ExtOp
ALUctr<2:0>
x
x
Add Subtract
0
Or
1
Add
1
Add
x
Subtract
ALUctr<2>
0
0
0
0
1
ALUctr<1>
1
ALUctr<0>
26
0
MemtoReg
OR: 001
ADD: 010
SUB: 110
31
1
21
16
R-type
op
rs
rt
I-type
op
rs
rt
CS 61C discussion 11 (17)
11
rd
6
shamt
immediate
0
funct
add, sub
ori, lw, sw, beq
Jaein Jeong 2002
Writing controls in Boolean formula
° Express following variables in Boolean formula of
OPCode and Func
• Add = OP[5]*OP[4]*OP[3]*OP[2]*OP[1]*OP[0]
*F[5] *F[4] *F[3] *F[2] *F[1] *F[0]
• Sub =
• Ori =
• Lw
=
• Sw
=
• Beq =
CS 61C discussion 11 (18)
Jaein Jeong 2002
Writing controls in Boolean formula
° Express following variables in Boolean formula of
Add, Sub, Ori, Lw, Sw, Beq, OPCode, or Func
• RegDst
= Add + Sub
• ALUSrc
=
• MemtoReg =
• RegWrite =
• MemWrite =
• nPCsel
=
• ExtOp
=
• ALUctr<2>= Sub + Beq
• ALUctr<1>=
• ALUctr<0>=
CS 61C discussion 11 (19)
Jaein Jeong 2002