Transcript Document

EE544/AEEE561 – Advanced
Digital Systems Design
Dr. Konstantinos Tatas
[email protected]
http://staff.fit.ac.cy/com.tk
Outcomes
• Understand all steps in the digital system design and
implementation process.
• design digital systems using Hardware Description
Languages
• Identify the available design, synthesis and implementation
options and trade-offs between performance, area and
power consumption
• develop testbenches to verify their designs
• Identify and resolve possible metastability and
synchronization issues in digital design
• Incorporate design reuse practices into their designs
• Use EDA tools to implement digital systems in FPGA
technology
• Keep up with current developments in digital design
methodologies and tools
Course Outline
• Combinational and sequential design practices – State
machines, Synchronous and asynchronous design.
• Synchronous Design Methodology – Clock skew –
Asynchronous inputs – Clock Gating - Metastability –
Reliable Synchronization of high-speed data transfers
• Design for performance, design for area, design for low
power consumption
• RTL design using Hardware Description Languages –
Verilog
• Digital system verification – Simulation (eventbased/cycle-based/transaction-based/emulation/AMS
simulation) – Equivalence checking – Static timing
verification – Rapid prototyping
• RTL Synthesis for ASIC and FPGAs - RTL coding
practices for synthesis
• Hardware accelerators – IP block design for reuse
• Testing and Design for Testability (DFT) fundamentals –
Built-In Self-Test (BIST)
Textbooks and References
• J. F. Wakerly, Digital Design: Principles and
Practices, Prentice Hall, 2003.
• Michael D. Ciletti, “Advanced Digital Design
with the Verilog HDL”, Prentice Hall, 2004
• Michael Keating, Russell John Rickford,
Pierre Bricaud, “Reuse Methodology
Manual for System-On-A-Chip Designs”,
Springer, 2006
Assessment
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Exam: 40%
Assignment 1: Paper writing/review (25%)
Assignment 2: Group project (25%)
Test: 10%
Weekly Breakdown
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Week 1: Digital Revision
Week 2: Synchronous Design
Week 3: Design flow – Paper review assignment
Week 4: Verilog
Week 5: Verilog
Week 6: Verilog /paper review presentation
Week 7: Verification
Week 8: Test
Week 9: Logic Synthesis/Design for reuse
Week 10: Assignment/Group project specifications
Week 11: Assignment/Group project review – Case study
part 1
• Week 12: Assignment/Group project review – Case study
part 2
• Week 13: Assignment/Group project assessment - Revision
The Binary Numbering System
• Digital systems and computers use the Binary system because it has only
two states (0 and 1)
• A number in the Binary system is expressed by the following expression:
(dndn-1…d1d0)2 = (dnX2n )+ (dn-1X2n-1) + …+ (d1X21) +( d0X20)
Where d = {0,1}
Examples:
• (1011)2 = (1X23 )+(0X22)+(1X21) +(1X20) = 8+0+2+1= (11)10
• (10110)2 = (1X24 )+(0X23)+(1X22) +(1X21) +(0X20) = 16+0+4+2+0= (22)10
• (101100)2=(1X25)+(0X24)+(1X23)+(1X22)+(0X21)+(0X20)=32+0+8+4+0+0=
(44)10
The Binary Numbering System (Cont.)
•
•
•
•
•
•
•
•
A binary digit is called the BIT (BInary digiT).
A group of eight bits is called the BYTE.
The leftmost bit of a number is called the Most Significant Bit (MSB).
The rightmost bit of a number is called the Least Significant Bit (LSB).
N
A binary system with N bits can represent the numbers from 0 to 2 -1.
N
In a binary system with N digits there are 2 different combinations.
A binary number is multiplied by two, if we append a zero at the LSB.
Prefixes in the binary system:
10
2 = 1,024 = 1K (Kilo)
20
2 = 1,024 X 1,024 = 1,048,576 = 1M (Mega)
Powers of 2:
0
2 =1
1
2 =2
2
2 =4
3
2 =8
4
2 = 16
5
2 = 32
6
2 = 64
7
2 = 128
8
30
2 = 256
40
2 = 512
2 = 1G (Giga)
2 = 1T (Tera)
9
10
2 =1024=1
K
16
2 = 65536
Negative Number Representation: Two’s Complement
• If the number is positive then the two’s complement is the same as the SM.
If the number is negative then the two’s complement is obtained by adding
1to the magnitude bits of the one’s complement. The sign bit is unchanged.
Sign bit
(+38)10 = (00100110)SM:8 = (00100110)2's C:8
Sign bit
(-38)10 = (11011001)1's C:8 = (11011010)2's C:8
Magnitude
Sign bit
(00101011)2's C:8 = (00101011)SM:8 = (+43) 10
Magnitude
Magnitude
+1
Sign bit
(11010101)2's C:8 = (10101011)SM:8 = (-43) 10
Magnitude
+1
• The two’s complement is widely used in computers to represent signed
integers. In most languages such as Pascal and C an integer variable is
represented in a 16-bit two’s complement representation.
Basic Logic Gates
Buffer
A
AND
X
A
B
OR
X
X= A
X= A B
A X
0 0
1 1
A
0
0
1
1
B
0
1
0
1
X
0
0
0
1
EX-OR
A
B
X
X= A+ B
A
0
0
1
1
B
0
1
0
1
X
0
1
1
1
A
B
X
X= A+ B
A
0
0
1
1
B
0
1
0
1
X
0
1
1
0
Logic
Function
Gate
Symbol
Logic
Expression
Truth
Table
Basic Logic Gates with Inverted Outputs
NOT
A
NAND
X
A
B
NOR
X
X= A
X= A B
A X
0 1
1 0
A
0
0
1
1
B
0
1
0
1
X
1
1
1
0
EX-NOR
A
B
X
X= A+ B
A
0
0
1
1
B
0
1
0
1
X
1
0
0
0
A
B
X
X= A+ B
A
0
0
1
1
B
0
1
0
1
X
1
0
0
1
Circuit Implementation of a Logic Expression with Gates
Logic Diagram with Gates
Logic Function
X = A + BC
A
B
X
B
C
BC
Logic Diagram with Gates
Logic Function
X = (A + B)C
A
B
C
A+B
B
X
Truth Tables
Truth table of a logic circuit is a table showing all the possible input combinations with
the corresponding value of the output.
Examples:
(a) Show the truth table of a 3-input circuit
that gives at its output a logic 1 if the input
forms a number between 3 and 6.
Inputs
A B C
(b) Show the truth table of the logic expression:
X = (AB + C)(A + C)
Output
X
A
B
C
AB
C
AB + C
A+ C
X = (AB+C)(A+C)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
2
0
1
0
0
0
1
0
0
1
1
1
1
3
0
1
1
1
0
1
1
0
0
0
0
0
4
1
0
0
1
1
0
0
0
1
1
1
1
5
1
0
1
1
1
0
1
0
0
0
1
0
6
1
1
0
1
1
1
0
1
1
1
1
1
7
1
1
1
0
1
1
1
1
0
1
1
1
Logic expression and truth table of a logic circuit
A
B
A
B
C T1 T2 T3 T4 X
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
T1 =
T3 =
C
T2 =
X
T4 =
Logic Expression: X =
SoP Form: X =
PoS Form: X =
Analyzing a logic circuit using timing diagrams
T1 =
A
T4 =
B
C
A
B
C T1 T2 T3 T4 X
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
T2 =
T3 =
X
Logic 1
Logic 0
A
B
C
X
Decoders
•
•
•
A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of
outputs ‘m’, where m= 2n
Only one of the outputs is enabled at a time. The output enabled is the one specified by
the binary number formed at the inputs of the decoder.
On the circuit below, the inputs of the decoder are connected on three switches, forming
the number 5 [(101)2], thus only LED #5 will be ON
1
1
1
0
0
0
0 1
0 1
0 1
0
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
Y7
1
2
3
4
5
6
7
2 to 4 Line Decoder:
2-to-4 Line Decoder
A1 A0 Y0 Y1 Y2 Y3
Y0 = A1 A 0
0
0
1
0
0
0
Y1 = A 1 A 0
Y1
0
1
0
1
0
0
Y2 = A1 A 0
Y2
1
0
0
0
1
0
Y3 = A1 A 0
1
1
0
0
0
1
Logic
Expressions
2/4 DEC
Y0
A1
A0
Y3
Logic Symbol
Truth Table
Y0
A1
Y1
Y2
A0
Y3
Logic Circuit
2-to-4 Line Decoder with Enable Input
2/4 DEC
E A1 A0 Y0 Y1 Y2 Y3
A1
Y0
0
X
X
0
0
0
0
A0
Y1
1
0
0
1
0
0
0
E
Y0 = E A1 A 0
Y1 = E A 1 A 0
Y 2 = E A1 A 0
Y2
1
0
1
0
1
0
0
Y3
1
1
0
0
0
1
0
Y3 = E A 1 A 0
1
1
1
0
0
0
1
Logic
Expressions
Logic Symbol
Y0
A1
Truth Table
Y1
E
Y2
A0
Y3
Logic Circuit
Internal structure of a 2-to-1
multiplexer.
• The design of a 2-to-1 multiplexer is shown below.
• If S=0 then the output “Y” has the same value as the input “I0”
• If S=1 then the output “Y” has the same value as the input “I1”
2-to-1 Multiplexer
2/1 MUX
S
I1
I0
Y
I0
0
0
0
0
I1
0
0
1
1
S
0
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
0
Y
Logic Symbol
S
Y
1
0
1
0
0
I0
1
1
0
1
1
I1
1
1
1
1
Logic Function
Truth Table
I0
I1I0
S
00 01 11 10
Y = S I0 + S I1
Logic Expression
1/2 Dec.
S
Y
I1
Logic Circuit
4-to-1 Multiplexer (MUX)
I0
I0
I1
I2
4-to-1
MUX
I1
O
2-to-1
MUX
2-to-1
MUX
S0
I3
I2
I3
2-to-1
MUX
S1
S1 S0
S1 S0 O
0 0 I0
0
1
I1
1
1
0
1
I2
I3
O
A
B Cin Cout Sum
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Truth Table
Sum
B
Cin
Cout
1-Bit Full Adder using gates
A
3/8 Dec.
A
Y0
B
B
Y1
C
Y2
A B Cin
Cout
Sum
Logic Symbol
8/1 Mux
I0
0
I1
0
I2
1
I3
0
I4
1
I5
0
4/1 Mux
I0
1
I6
A
I1
1
I7
S2 S 1 S0
A
I2
1
I3
S1 S0
1-bit Full Adder
A
Cin
1-Bit F.A.
0
En
Y
Cout
A
B
Y
Cout
B
Cin
Cin
Y3
0
S2 S 1 S0
I0
Y4
1
I1
A
S1 S0
I0
Y5
1
I2
A'
I1
Y6
0
I3
A'
I2
Y7
1
I4
A
0
I5
I3
4/1 Mux
0
I6
1
I7
8/1 Mux
Cout
Sum
1-Bit Full Adder using a decoder
Y
Sum
Y
Sum
1-Bit Full Adder using 4/1 multiplexers
1-Bit Full Adder using 8/1 multiplexers
4-bit Full Adder (Ripple-Carry
Adder)
A3 B3
A2 B2
A1 B 1
A0 B 0
• To obtain a 4-bit full adder we cascade four
0
1-bitA full
connecting
the
Carry
B C adders,
A B by
C
A B C
A B
C
F.A.
1-Bit F.A.In of
Out 1-Bit
bitF.A.of bit 1-Bit
column
M1-BittoF.A.the Carry
C
Sum
C
Sum
Sum
C
Sum
the bit
column
M+1,
as Cshown
below.
The
Cout
Carry
In of the Least Significant column is
S3
S2
S1
S0
set to zero.
in
out
in
out
in
out
in
out
• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder
shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.
Review questions
• How many input/output signals are present in a
– 5-to-32 decoder?
– 32-to-1 MUX?
– 32-bit Ripple-Carry Adder (RCA)?
• How many 2-to-1 MUXs are required to build a 32-to-1 MUX?
• Design a logic unit with 2 data inputs (A, B), three select inputs
(S2, S1, S0) and the following specifications:
S2
S1
S0
O
0
0
0
A AND B
0
0
1
A OR B
0
1
0
A XOR B
0
1
1
A NAND B
1
0
0
A NOR B
1
0
1
A XNOR B
1
1
0
A΄
1
1
1
B΄
The Toggle (T) Edge Triggered Flip Flop
The T edge triggered flip flop can be obtained by connecting the J with the K
inputs of a JK flip directly. When T is zero then both J and K are zero and the
Q output does not change. When T is one then both J and K are one and the Q
output will change to the opposite state, or toggle.
Positive Edge T Flip Flop
T
J
Q
Negative Edge T Flip Flop
Q
T
CLK
T
Q
CLK
Q
Q
Q
K
Q
Q
T
QN+1
Function
X
Q
0
Q
1
Q΄
CLK
K
Logic Symbol
J
CLK
Q
Q
T
QN+1
Function
X
0
Q
Q
1
Q΄
Logic Symbol
T
Q
CLK
Q
CLK
D and T Edge Triggered Flip Flops :- Example
Complete the timing diagrams for :
(a) Positive Edge Triggered D Flip Flop
(b) Positive Edge Triggered T Flip Flop
(c) Negative Edge Triggered T Flip Flop
(d) Negative Edge Triggered D Flip Flop
(b)
(a)
CLK
CLK
D
D
Q
Q
(d)
(c)
CLK
CLK
T
T
Q
Q
Finite state machine block diagram
PREVIOUS STATE
STATE MEMORY
D
SET
Q
OUTPUTS
NEXT
STATE
Q
...
INPUTS
NEXT STATE
LOGIC
CLR
D
SET
CLR
OUTPUT LOGIC
Q
Q
CLK
• State memory: Set of n flip-flops that hold the state of the
machine (up to 2^n distinct states)
• Next state logic: Combinational circuit that determines
the next state as a function of the current state and the
input
• Output logic: Combinational circuit that determines the
output as a function of the current state and the input
Finite State Machine types
PREVIOUS STATE
STATE MEMORY
– State = output state
machine: A Moore type
FSM where the current
state is the output
SET
Q
OUTPUTS
NEXT
STATE
CLR
Q
OUTPUT LOGIC
...
INPUTS
COMBINATIONAL
LOGIC
D
SET
CLR
Q
Q
CLK
PREVIOUS STATE
STATE MEMORY
D
SET
Q
OUTPUTS
COMBINATIONAL
LOGIC
CLR
Q
OUTPUT LOGIC
...
INPUTS
NEXT
STATE
D
SET
CLR
Q
Q
CLK
PREVIOUS STATE
STATE MEMORY
D
INPUTS
COMBINATIONAL
LOGIC
NEXT
STATE
SET
CLR
D
SET
CLR
CLK
Q
Q
...
• Mealy machine: The
output depends on the
current state and input
• Moore machine: The
output depends only on
the current state
D
Q
Q
OUTPUTS
State diagram
A state diagram represents the states as circles and the
transitions between them as arrows annotated with inputs and
outputs
1/0
0/0
0/1
00
10
0/1
1/0
0/1
1/0
1/0
01
11
Analysis of FSMs with D flip-flops
• Determine the next state and output
functions
• Use the functions to create a state/output
table that specifies every possible next state
and output for any combination of current
state and input
EXAMPLE
X
D
SET
CLR
D
CP
SET
CLR
Q
A
Q
A’
Q
B
Q
B’
Y
Next state equations and state table
for example
• A+=Ax+Bx
• B+=A΄x
• Y=(A+B)x΄
A
B
x
A+
B+
y
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
• A+=Ax+Bx
• B+=A΄x
• Y=(A+B)x΄
X
D
SET
CLR
D
CP
SET
CLR
Q
A
Q
A’
Q
Q
B
B’
Y
A
B
x
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A+
B+
y
Sequential circuit design methodology
• From the description of the functionality or the
state/timing diagram find the state table
• Encode the states if the state table contains letters
• Find the necessary number of flip-flops
• Select flip/flop type
• From the state table, find the excitation tables and
output tables
• Using Karnaugh maps find the flip-flop input
logic expressions
• Draw the circuit logic diagram
Algorithm Implementation
• Often we have to implement an algorithm in hardware
instead of software
• Algorithm is a well defined procedure consisting of a
finite number of steps to the solution of a problem.
• It is often hard to translate the algorithm into an FSM.
• ASMs can serve as stand-alone sequential network
model.
Algorithmic State Machine
•Used to graphically describe the operations of an FSM more concisely
•Resembles conventional flowcharts – differs in
interpretation.
•Conventional flowchart – sequential way of
representing procedural steps and decision paths
for algorithm
-No time relations incorporated
•ASM chart – representation of sequence of
events together with timing relations between
states of sequential controller and events
occurring while moving between steps
ASM Chart
•Three basic elements: state box, decision
box and conditional box
-State and decision boxes used in conventional
flowcharts
-Conditional box characteristic to ASM
•State box
-Used to indicate states in control sequence
•Register operations and output signals used to
control generation of next state written
State box
•Represents one state in the ASM.
•May have an optional state output list.
•Single entry.
•Single exit to state or decision boxes.
State Box
State name T3
•Binary code of T3 – 011
•Register operation R <- 0
•START – name of
outputs signal generated
in this stage
Decision box
• Provides for next alternatives and
conditional outputs.
• Conditional output based on logic
value of Boolean expression involving
external input variables and status
information.
• Single entry.
• Dual exit, denoting if Boolean
expression is true or false.
• Exits to decision, state or conditional
boxes.
Decision Box
•Input condition subject to
test inside diamond shape
box
•Two or more outputs
represent exit paths
dependant on value of
condition in decision box
•Two paths for binary based
conditions
Conditional output box
• Provides a listing of output variables
that are to have a value logic-1, i.e.,
those output variables being
asserted.
• Single entry from decision box.
• Single exit to decision or state box.
•In state T1
Output signal START
generated
Status of input E
checked
•If E = 1, R <- 0,
otherwise remains
unchanged
•Conditional
operation executed
depending on result
of coming from
decision box
Conditional Box
ASM Block
• Consists of the interconnection of a single
state box along with one or more decision
and/or conditional boxes.
• It has one entry path which leads directly
to its state box, and one or more exit
paths.
• Each exit path must lead directly to a
state, including the state box in itself.
• A path through an ASM block from its state
box to an exit path is called a link path.
Timing Considerations
All sequential elements in datapath and control
path controlled by master-clock generator.
Does not necessarily imply single clock in design.
•Multiple clocks can be obtained through division of clock
signals from master-clock generator.
•Not only internal signals, but also inputs
synchronized with clock.
•Normally, inputs supplied by other devices working
with the same master clock.
•Some inputs can arrive asynchronously
Difficult to handle by synchronous designs, require
asynchronous glue-logic.
•In conventional flowchart, evaluation
of each chart element takes one clock
cycle
Step 1: Reg A incremented
Step 2: Condition E evaluated
Step 3: Based on evaluation results,
state
T2, T3 or T4 entered
•In ASM the entire block considered
as one unit
•All operations within block occurring
during single edge transition
The next state evaluated during the
same clock
System enters next state T2, T3 or T4
during transition of next clock
ASM
Block
ASM Block
• An ASM block describes the operation of the system
during the state time in which it is in the state
associated with the block.
• The outputs listed in the state box are asserted.
• The conditions indicated in the decision boxes are
evaluated simultaneously to determine which link
path is to be followed.
• If a conditional box is found in the selected path
then the outputs found in its output list are asserted.
• Boolean expression may be written for each link
path. The selected link paths are those that evaluate
to logic-1.
T0
Example 2
0
x
1
T1
0
x
• Extract the FSM
diagram from the
ASM diagram
T2
0
F
1
T4
T3
0
E
1
T6
T7
T5