Transcript Introduction to Giano Alessandro Forin Microsoft Research Take-aways • Giano is the first Real-Time Simulation Framework for hardware-software co-development • Uses Microsoft Visio as the graphing and.

Introduction
to
Giano
Alessandro Forin
Microsoft Research
Take-aways
• Giano is the first Real-Time Simulation Framework for
hardware-software co-development
• Uses Microsoft Visio as the graphing and execution UI
• Configurations are Platform XML files
• Nodes in the graph are separate, user-defined DLLs
• Properties are user-defined and node-specific
• Lots of functionality pre-built into the base framework
• 70+ working modules, 20+ systems, 4 years internal use
• Source, free for academic use at
http://research.microsoft.com/downloads
Hw/Sw Co-Development?
a) Develop or synthesize hardware and
software at the same time
b) Simulate a full system before it is ready
c) Use C-models and/or HDL-models to
define behaviors
d) All of the above
 Giano
CPU
MEM
Giano process
ModelSim process
ARM: At91m63200
Xilinx: Spartan3
Start = TheCounter->Value;
...compute...
End = TheCounter->Value;
I/O
module test;
always @(posedge clock)
counter = counter + 1;
FPGA: vvp.dll
PLI plug-in (VPI)
NamedPipe “GIANO”
NamedPipe client
Optional: Icarus
Verilog Interpreter
PLI plug-in (VPI)
Optional: external
devices (LabView)
AES components, sw/hw
Test program and
data
ICipher
implementation
AES
component
Base RTOS
ARM Microcontroller
Xilinx FPGA
Real-Time Simulation
• Definition
Realize a software system that matches the
temporal behavior of the hardware+software
system being simulated, using the same timeordered sequence of inputs
• Applicable to hybrid hw+sw simulators too
• Requires:
– Clock adaptation
– I/O adaptation
Clock Adaptation
Problem: Output a character every second
• Timer too slow/fast?  Incorrect
• Host load changes?  Erratic
Solution: Rate-limit the clock using
introspection and adaptation
Rate-limiting the Clock
1. Every M (10**3) clock ticks spin idle for D
microseconds
2. Every N (10**6) clock ticks check the
actual frequency against the target
frequency, adjust the delay D
Adjusting the Delay factor
Delay Calibration
600
500
400
DelayFactor
300
ns
TgtIpsTime
CurIpsTime
200
DelayAdjust
100
0
time(sec)
108
104
20
96
92
88
83
79
75
71
67
64
60
57
-100
Effect on IPS
Effective IPS
20000000
18000000
16000000
14000000
Target
10000000
Current
8000000
6000000
4000000
2000000
tim e(sec)
10
8
10
4
20
96
92
88
83
79
75
71
67
64
60
0
57
IPS
12000000
I/O adaptation
Problem: 9600 baud serial line
• From disk trace?  too fast
• From user?  too slow
• From real serial line?  depends
Solution:
– Link to rate-limited clock
– Adapt using events and notifications
Example: Programmable Timer
void TcDevice::Event(GIANO_EVENT *Event)
{
PTC_STATE State = &this->TcState;
UINT32 BaseCount = (UINT32) Event->Arg2;
if (Event == &Notification)
{
CalibrateTc( (UINT32) Event->Arg1 );
return;
}
// trigger interrupt if enabled
State->Control |= TCCT_INTERRUPT;
if (State->Control & TCCT_ENABLE)
ParentBus->Interrupt( InterruptNumber, true);
…..
Take-aways
• Giano is the first Real-Time Simulation Framework
for hardware-software co-development
• Uses Microsoft Visio as the graphing and execution UI
• Configurations are Platform XML files
• Nodes in the graph are separate, user-defined DLLs
• Properties are user-defined and node-specific
• Lots of functionality pre-built into the base framework
• 70+ working modules, 20+ systems, 4 years internal use
• Source, free for academic use at
http://research.microsoft.com/downloads
Visio Diagrams
Atmel EB63 Evaluation Board
Multi-processors
Apple Power Mac G5
Take-aways
• Giano is the first Real-Time Simulation Framework for
hardware-software co-development
• Uses Microsoft Visio as the graphing and execution
User Interface
• Configurations are Platform XML files
• Nodes in the graph are separate, user-defined DLLs
• Properties are user-defined and node-specific
• Lots of functionality pre-built into the base framework
• 70+ working modules, 20+ systems, 4 years internal use
• Source, free for academic use at
http://research.microsoft.com/downloads
Per-node Properties
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Create/edit as Visio “Custom Properties”
Values are Unicode strings and numbers
Only the “Implementation” is required
Any property can be overridden on the
command line
Giano Engine
• Parses the XML configuration graph
• Instantiates the modules as DLLs
• Exports a few support classes to the
modules
Platform XML
<?xml version='1.0'?>
<Configuration name="MyConfiguration">
<CPU name="Cpu1">
<Property name="CpuType" value="ARM" />
<Property name="Implementation" value=“arm" />
<ConnectsTo name="RootBus" />
</CPU>
<BUS name="RootBus">
<Property name="BusType" value="RootBus" />
<Property name="Implementation" value=“amba" />
<ConnectsTo name="Cpu1" />
<ConnectsTo name="Memory" />
</BUS>
<Memory name="Memory">
<Property name="MemoryType" value="RAM" />
<Property name="Implementation" value="memory" />
<Property name="StartAddress" value="0" />
<Property name="Size" value="2097152" />
<ConnectsTo name="RootBus" />
</Memory>
Take-aways
• Giano is the first Real-Time Simulation Framework for
hardware-software co-development
• Uses Microsoft Visio as the graphing and execution UI
• Configurations are Platform XML files
• Nodes in the graph are separate, user-defined DLLs
• Properties are user-defined and node-specific
• Lots of functionality pre-built into the base framework
• 70+ working modules, 20+ systems, 4 years internal use
• Source, free for academic use at
http://research.microsoft.com/downloads
Core Functionalities
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Central clock, linked to CPU #0
Real-Time calibration, both CPUs and I/O
Eventing and dynamic re-calibration
Mapping to the host’s physical devices
Large simulated guest memory (512 MB and up)
Symbol tables with load/unload
Tracing and basic-block profiling
Graph management, with hot-plugging
MP interlocks
CPUs
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ARM & Thumb, MIPS (both endians), PowerPC
SimpleScalar, PolyScalar, Cacti
In-Circuit Emulation (ICE), 2 JTAG
Traps, external interrupts, resets
Pluggable MMUs: one software, one in Verilog
All interpreters (so far), all MultiProc
Self-testing against “Oracle” machines
~20 Million instructions per second
Settable lower speed (25MHz ~> 5 MIPS)
Busses
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PCI, AGP, EBI, MPI, “root bus”
Test case generator (MIPS)
Optimized routing, always one-hop away.
Aliasing and multi-mapping
Interrupt routing
Support hot-plug/unplug of modules
Memory
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RAM, ROM, FLASH, Serial Flash
Boot images and overlays
Arbitrary transaction sizes
Accessible from any module (DMA!)
Buffer pinning
Large, contiguous virtual segment for best
performance
• Aliasing
Peripherals, examples
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2D-graphic, 2 LCDs, keyboard, mouse, sound card
A/D and D/A converters, gyroscope
Ethernet, FireWire, Serial lines
IDE and ATAPI disks
3 interrupt controllers and 3 timers
GPIO with buttons, LEDs, Serial Flash
Power/System management chips [with fan ]
FPGA interface to ModelSim/Icarus
Watchdog, “Debug” modules
“Do-nothing” module for unimplemented parts
Take-aways
• Giano is the first Real-Time Simulation Framework for
hardware-software co-development
• Uses Microsoft Visio as the graphing and execution UI
• Configurations are Platform XML files
• Nodes in the graph are separate, user-defined DLLs
• Properties are user-defined and node-specific
• Lots of functionality pre-built into the base framework
• 70+ working modules, 20+ systems, 4 years internal use
• Source, free for academic use at
http://research.microsoft.com/downloads