Transcript CS 61C: Great Ideas in Computer Architecture (Machine Structures) Traps, Exceptions, Virtual Machines Instructors: Randy H.

CS 61C: Great Ideas in Computer
Architecture (Machine Structures)
Traps, Exceptions, Virtual Machines
Instructors:
Randy H. Katz
David A. Patterson
http://inst.eecs.Berkeley.edu/~cs61c/Sp11
11/6/2015
Spring 2011 -- Lecture #25
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11/6/2015
Spring 2011 -- Lecture #25
2
New-School Machine Structures Today’s
Big Idea: Memory Hierarchy Lecture
Software
• Parallel Requests
Assigned to computer
e.g., Search “Katz”
Hardware
Harness
• Parallel Threads Parallelism &
Assigned to core
e.g., Lookup, Ads
Achieve High
Performance
Smart
Phone
Warehouse
Scale
Computer
Virtual
Memory
Computer
• Parallel Instructions
>1 instruction @ one time
e.g., 5 pipelined instructions
• Parallel Data
>1 data item @ one time
e.g., Add of 4 pairs of words
• Hardware descriptions
All gates @ one time
11/6/2015
…
Core
Memory
Core
(Cache)
Input/Output
Instruction Unit(s)
Core
Functional
Unit(s)
A0+B0 A1+B1 A2+B2 A3+B3
Main Memory
Logic Gates
Spring 2011 -- Lecture #25
3
New-School Machine Structures Today’s
Lecture
Software
• Parallel Requests
Assigned to computer
e.g., Search “Katz”
Hardware
Harness
Smart
Phone
Warehouse
Scale
Computer
• Parallel Threads Parallelism &
Assigned to core
e.g., Lookup, Ads
Virtual
Machines
Achieve High
Traps
Performance
Computer
• Parallel Instructions
>1 instruction @ one time
e.g., 5 pipelined instructions
• Parallel Data
>1 data item @ one time
e.g., Add of 4 pairs of words
• Hardware descriptions
All gates @ one time
11/6/2015
…
Core
Memory
Core
(Cache)
Input/Output
Instruction Unit(s)
Core
Functional
Unit(s)
A0+B0 A1+B1 A2+B2 A3+B3
Main Memory
Logic Gates
Spring 2011 -- Lecture #25
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Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
Spring 2011 -- Lecture #25
5
Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
Spring 2011 -- Lecture #25
6
Protection + Indirection =
Virtual Address Space
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
stack
~ FFFF FFFFhex
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Page
Table
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Physical Memory
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Spring 2011 -- Lecture #25
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Protection + Indirection =
Virtual Address Space
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
stack
~ FFFF FFFFhex
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Page
Table
Stack 1
Heap 1
Static 1
Code 1
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Physical Memory
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Protection + Indirection =
Virtual Address Space
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
stack
~ FFFF FFFFhex
7
6
5
4
3
2
1
0
Page
Table
Stack 2
Heap 2
Static 2
Code 2
Stack 1
Heap 1
Static 1
Code 1
7
6
5
4
3
2
1
0
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Physical Memory
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Protection + Indirection =
Dynamic Memory Allocation
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
7
6
5
4
3
2
1
0
Page
Table
malloc(4097)
11/6/2015
stack
~ FFFF FFFFhex
Heap’ 1
Stack 2
Heap 2
Static 2
Code 2
Stack 1
Heap 1
Static 1
Code 1
7
6
5
4
3
2
1
0
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Physical Memory
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Protection + Indirection =
Dynamic Memory Allocation
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
7
6
5
4
3
2
1
0
Page
Table
malloc(4097)
11/6/2015
stack
~ FFFF FFFFhex
Stack’ 2
Heap’ 1
Stack 2
Heap 2
Static 2
Code 2
Stack 1
Heap 1
Static 1
Code 1
Physical Memory
Spring 2011 -- Lecture #25
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6
5
4
3
2
1
0
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Recursive function call
11
Protection + Indirection =
Controlled Sharing
stack
~ FFFF FFFFhex
heap
static data
code
~ 0hex
Application 1
Virtual Memory
7
6
5
4
3
2
1
0
Page
Table
Stack 2
Heap 2
Static 2
Stack 1
Heap 1
Static 1
Code
Physical Memory
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stack
~ FFFF FFFFhex
Spring 2011 -- Lecture #25
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6
5
4
3
2
1
0
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Shared Code Page
“X” Protection Bit
12
Protection + Indirection =
Controlled Sharing
~ FFFF FFFFhex
stack
heap
static data
~ 0hex
code
stack
~ FFFF FFFFhex
7
6
5
4
3
2
1
0
Page
Table
Application 1
Virtual Memory
Shared Globals
“RW” Protection
Bits
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Stack 2
Heap 2
Stack 1
Heap 1
Static
Code
Physical Memory
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6
5
4
3
2
1
0
Page
Table
heap
static data
~ 0hex
code
Application 2
Virtual Memory
Shared Code Page
“X” Protection Bit
13
Day in the Life of an
(Instruction) Address
PC
PA
PA
MEM
Instruction
No Cache, No Virtual Memory
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Day in the Life of an
(Instruction) Address
PC
VA (VPN, Offset)
TLB
PA (PPN, Offset)
Hit
PA
MEM
Instruction
No Cache, Virtual Memory, TLB Hit—Very Fast!
If locality works, this is the most common case!
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Day in the Life of an
(Instruction) Address
PC
VA (VPN, Offset)
TLB
PTBR
Page Table
Base Register
Miss
VPN
+
PA
(@Page
Table Entry)
MEM
PA (PPN, Offset)
PA
MEM
Instruction
No Cache, Virtual Memory, TLB Miss, Page Table Access
NOTE: Virtual Memory implemented before caches
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Day in the Life of an
(Instruction) Address
PC
VA (VPN, Offset)
TLB
PTBR
Page Table
Base Register
Miss
VPN
+
PA
(@Page
Table Entry)
D$
PA (PPN, Offset)
Hit
PA
MEM
Instruction
Physical Data Cache, Virtual Memory, TLB Miss, Page Table Access
VA caches are possible, but it’s complicated: see CS 162
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Day in the Life of an
(Instruction) Address
PC
VA (VPN, Offset)
TLB
PTBR
Page Table
Base Register
Miss
VPN
+
PA
(@Page
Table Entry)
D$
Miss
PA
PA (PPN, Offset)
PA
MEM
MEM
(@Page
Instruction
Table Entry)
Physical Data Cache, Virtual Memory, TLB Miss, Page Table Access
VA caches are possible, but it’s complicated: see CS 162
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Day in the Life of an
(Instruction) Address
VA (VPN, Offset)
PC
TLB
PTBR
Page Table
Base Register
+
Miss
VPN
PA
(@Page
Table Entry)
D$
Miss
PA
MEM
(@Page
Table Entry)
PA
(PPN,
Offset)
I$
Hit
Instruction
Physical Data & Instruction Cache, Virtual Memory, TLB Miss, Page Table Access
VA caches are possible, but it’s complicated: see CS 162
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Day in the Life of an
(Instruction) Address
VA (VPN, Offset)
PC
TLB
PTBR
Page Table
Base Register
+
Miss
VPN
PA
(@Page
Table Entry)
D$
Miss
PA
MEM
(@Page
Table Entry)
PA
(PPN,
Offset)PA
I$
Miss
MEM
Instruction
Day in the life of a data access is not too different
Physical Data & Instruction Cache, Virtual Memory, TLB Miss, Page Table Access
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Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
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Administrivia
•
•
•
•
Extra Credit due 4/24 – Fastest Matrix Multiply
F2F “Grading” of Project 4 in Lab this week
Final Review: Mon 5/2, 5 – 8PM, 2050 VLSB
Final Exam: Mon 5/9, 11:30-2:30PM,
100 Haas Pavilion
– Designed for 90 minutes, you will have 3 hours
– Comprehensive (particularly problem areas on
midterm), but focused on course since midterm:
lecture, lab, hws, and projects are fair game
– 8 ½ inch x 11 inch crib sheet like midterm
11/6/2015
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CS61c in the News!
•
•
•
•
•
•
•
•
•
•
•
•
NVIDIA Tegra 2 Processor with
1GHz Dual-core ARM Processor
1080p MPEG-4/H.264 Recording
and Playback
HDMI mirroring
4-inch WVGA screen
8-megapixel rear camera / 1.3megapixel front camera
7.1 multi-channel virtual surround
sound
8GB memory
microSD memory expandability
(up to 32GB)
Micro-USB connectivity
1,500 mAh battery
Supports Adobe Flash Player 10.1
11/6/2015
LG Optimus 2X Smart Phone
Theater-quality entertainment on a mobile device
“It’s Game Over for Single-core Smartphones.”
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President Obama @ FB Yesterday!
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Spring 2011 -- Lecture #25
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http://www.theonion.com/video/cias-facebook-program-dramatically-cut-agencys-cos,19753/
Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
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Historical Retrospective:
1960 versus 2010
• Memory used to be very expensive, and amount available
to the processor was highly limited
– Now memory is cheap: approx $20 per GByte in April 2011
• Many apps’ data could not fit in main memory, e.g.,
payroll
– Paged memory system reduced fragmentation but still
required whole program to be resident in the main memory
– For good performance, buy enough memory to hold your apps
• Programmers moved the data back and forth from the
diskstore by overlaying it repeatedly on the primary store
– Programmers no longer need to worry about this level of
detail anymore
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Demand Paging in Atlas (1962)
“A page from secondary
storage is brought into the
primary storage whenever
it is (implicitly) demanded
by the processor.”
Tom Kilburn
Primary memory as a cache
for secondary memory
User sees 32 x 6 x 512 words
of storage
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Primary
32 Pages
512 words/page
Central
Memory
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Secondary
(~disk)
32x6 pages
27
Demand Paging Scheme
• On a page fault:
– Input transfer into a free page is initiated
– If no free page available, a page is selected to be
replaced (based on usage)
– Replaced page is written on the disk
• To minimize disk latency effect, the first empty page
on the disk was selected
– Page table is updated to point to the new location of
the page on the disk
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Impact on TLB
• Keep track of whether page needs to be
written back to disk if it has been modified
• Set “Page Dirty Bit” in TLB when any data in
page is written
• When TLB entry replaced, corresponding Page
Dirty Bit is set in Page Table Entry
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Address Translation: Putting it all Together
Virtual Address
Restart instruction
hardware
hardware or software
software
TLB
Lookup
miss
hit
Protection
Check
Page Table
Walk
the page is
 Memory
Page Fault
(OS loads page)
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 memory
Update TLB
denied
Protection
Fault
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SEGFAULT
permitted
Physical
Address
(to cache)
30
Address Translation in CPU Pipeline
PC
Inst
TLB
Inst.
Cache
TLB miss? Page Fault?
Protection violation?
D
Decode
E
+
M
Data
TLB
Data
Cache
W
TLB miss? Page Fault?
Protection violation?
• Software handlers need restartable exception on TLB fault
• Handling a TLB miss needs a hardware or software mechanism
to refill TLB
• Need mechanisms to cope with the additional latency of a TLB:
– Slow down the clock
– Pipeline the TLB and cache access
– Virtual address caches (indexed with virtual addresses)
– Parallel TLB/cache access
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Impact of Paging on AMAT
• Memory Parameters:
–
–
–
–
L1 cache hit = 1 clock cycles, hit 95% of accesses
L2 cache hit = 10 clock cycles, hit 60% of L1 misses
DRAM = 200 clock cycles (~100 nanoseconds)
Disk = 20,000,000 clock cycles (~ 10 milliseconds)
• Average Memory Access Time (with no paging):
– 1 + 5%*10 + 5%*40%*200 = 5.5 clock cycles
• Average Memory Access Time (with paging) =
– AMAT (with no paging) + ?
– 5.5 + ?
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Student Roulette?
Impact of Paging on AMAT
• Memory Parameters:
–
–
–
–
L1 cache hit = 1 clock cycles, hit 95% of accesses
L2 cache hit = 10 clock cycles, hit 60% of L1 misses
DRAM = 200 clock cycles (~100 nanoseconds)
Disk = 20,000,000 clock cycles (~ 10 milliseconds)
• Average Memory Access Time (with paging) =
– 5.5 + 5%*40%*(1-HitMemory)*20,000,000
• AMAT if HitMemory = 99.9%?
– 5.5 + 0.02 * .001 * 20,000,000 = 405.5
• AMAT if HitMemory = 99.9999%
– 5.5 + 0.02 * .000001 * 20,000,000 = 5.9
11/6/2015
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Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
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§4.9 Exceptions
Exceptions and Interrupts
• “Unexpected” events requiring change in flow of
control
– Different ISAs use the terms differently
• Exception
– Arises within the CPU
• e.g., Undefined opcode, overflow, syscall, …
• Interrupt
– From an external I/O controller
• Dealing with them without sacrificing performance is
difficult
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Handling Exceptions
• In MIPS, exceptions managed by a System Control
Coprocessor (CP0)
• Save PC of offending (or interrupted) instruction
– In MIPS: save in special register called
Exception Program Counter (EPC)
• Save indication of the problem
– In MIPS: saved in special register called Cause register
– We’ll assume 1-bit
• 0 for undefined opcode, 1 for overflow
• Jump to exception handler code at address
8000 0180hex
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Exception Properties
• Restartable exceptions
– Pipeline can flush the instruction
– Handler executes, then returns to the instruction
• Refetched and executed from scratch
• PC saved in EPC register
– Identifies causing instruction
– Actually PC + 4 is saved because of pipelined
implementation
• Handler must adjust PC to get right address
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Handler Actions
• Read Cause register, and transfer to relevant
handler
• Determine action required
• If restartable exception
– Take corrective action
– use EPC to return to program
• Otherwise
– Terminate program
– Report error using EPC, cause, …
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Exceptions in a Pipeline
• Another kind of control hazard
• Consider overflow on add in EX stage
add $1, $2, $1
– Prevent $1 from being clobbered
– Complete previous instructions
– Flush add and subsequent instructions
– Set Cause and EPC register values
– Transfer control to handler
• Similar to mispredicted branch
– Use much of the same hardware
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Exception Example
• Exception on add in
40
44
48
4C
50
54
58
…
sub
and
or
add
slt
lw
lui
$11,
$12,
$13,
$1,
$15,
$16,
$14,
$2, $4
$2, $5
$2, $6
$2, $1
$6, $7
50($7)
1000
• Handler
80000180 sw
80000184 sw
…
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$25, 1000($0)
$26, 1004($0)
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Exception Example
Time (clock cycles)
Reg
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
ALU
D$
Reg
I$
Reg
ALU
D$
Reg
Reg
ALU
I$
D$
ALU
11/6/2015
Reg
ALU
O slt
r
d lw
e
r lui
I$
ALU
I and
n
s or
t
r. add
D$
I$
Spring 2011 -- Lecture #25
Reg
42
Exception Example
Time (clock cycles)
Reg
Reg
D$
Reg
I$
Reg
ALU
D$
Reg
I$
Reg
ALU
D$
Reg
I$
Reg
ALU
D$
Reg
Reg
ALU
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I$
D$
ALU
O (bubble)
r
d (bubble)
e
r sw
Reg
ALU
I$
I and
n
s or
Flushtadd, slt, lw
r. (bubble)
D$
Spring
2011 -- Lecture #25
1st instruction of
handler
Save PC+4 into EPC
I$
Reg
43
Multiple Exceptions
• Pipelining overlaps multiple instructions
– Could have multiple exceptions at once
– E.g., Page fault in LW same clock cycle as Overflow of following
instruction ADD
• Simple approach: deal with exception from earliest
instruction, e.g., LW exception serviced 1st
– Flush subsequent instructions
• Called Precise exceptions
• In complex pipelines:
– Multiple instructions issued per cycle
– Out-of-order completion
– Maintaining precise exceptions is difficult!
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Imprecise Exceptions
• Just stop pipeline and save state
– Including exception cause(s)
• Let the software handler work out
– Which instruction(s) had exceptions
– Which to complete or flush
• May require “manual” completion
• Simplifies hardware, but more complex handler software
• Not feasible for complex multiple-issue out-of-order
pipelines to always get exact instruction
• All computers today offer precise exceptions—affects
performance though
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Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
Spring 2011 -- Lecture #25
46
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47
Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
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Beyond Virtual Memory
• Even greater protection than virtual memory
– E.g., Amazon Web Services allows independent tasks run
on same computer
• Can a “small” operating system simulate the hardware
of some machine, so that
– Another operating system can run in that simulated
hardware?
– More than one instance of that operating system run on
the same hardware at the same time?
– More than one different operating system can share the
same hardware at the same time?
• Answer: Yes
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Solution – Virtual Machine
• A virtual machine provides interface identical
to underlying bare hardware
– I.e., all devices, interrupts, memory, page
tables, etc.
• Virtualization has some performance impact
– Feasible with modern high-performance computers
• Examples
–
–
–
–
11/6/2015
IBM VM/370 (1970s technology!)
VMWare
Xen (used by AWS)
Microsoft Virtual PC
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Randy’s Personal Experience
VM/370, circa 1973
• Summer internship @ CoNY Dept Welfare
Service
• VM/370: allows programmer to write channel
programs, basically machine instructions
(CCW—channel control words) to directly
control
I/O devices
• Let’s try to ring the computer’s console bell
• Terminal log prints out the following:
!!!!RRRR....RING....GGGG!!!!
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Virtual Machines
• Host Operating System:
– OS actually running on the hardware
– Together with virtualization layer, it simulates
environment for …
• Guest Operating System:
– OS running in the simulated environment
• The resources of the physical computer are
shared to create the virtual machines
– Processor scheduling by OS can create the appearance
that each user has own processor
– Disk partitioned to provide virtual disks
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Virtual Machine Monitor
• Maps virtual resources to physical resources
– Memory, I/O devices, CPUs
• Guest code runs on native machine in user
mode
– Traps to VMM on privileged instructions and
access to protected resources
• Guest OS may be different from host OS
• VMM handles real I/O devices
– Emulates generic virtual I/O devices for guest
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Example: Timer Virtualization
• In native machine, on timer interrupt
– OS suspends current process, handles interrupt,
selects and resumes next process
• With Virtual Machine Monitor
– VMM suspends current VM, handles interrupt, selects
and resumes next VM
• If a VM requires timer interrupts
– VMM emulates a virtual timer
– Emulates interrupt for VM when physical timer
interrupt occurs
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Virtual Machine
Instruction Set Support
• Similar to what need for Virtual Memory
• User and System modes
• Privileged instructions only available in system
mode
– Trap to system if executed in user mode
• All physical resources only accessible using
privileged instructions
– Including page tables, interrupt controls, I/O registers
• Renaissance of virtualization support
– Current ISAs (e.g., x86) adapting, following IBM’s path
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Agenda
•
•
•
•
•
•
•
Virtual Memory Revisted
Administrivia
Demand Paging
Exceptions, Traps, Interrupts
Technology Break
Virtual Machines
Summary
11/6/2015
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And in Conclusion, …
• Virtual Memory, Paging really used for
Protection, Translation, Some OS optimizations
– Not really routinely paging to disk
– Can think of as another level of memory hierarchy,
but not really used like caches
• Virtual Machines as even greater level of
protection to allow greater level of sharing
– Enables fine control, allocation, pricing of Cloud
Computing
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Peer Instruction: Match the Phrase
Match the memory hierarchy element on the left
with the closest phrase on the right:
1. L1 cache
a. A cache for page table entries
2. L2 cache
b. A cache for a main memory
3. Main memory c. A cache for disks
4. TLB
d. A cache for a cache
RED) 1 a, 2 b, 3 c, 4 d
PINK) 1 b, 2 d, 3 c, 4 a
ORG) 1 a, 2 b, 3 d, 4 c
GRN) 1 b, 2 d, 3 a, 4 c
BLU) 1 d, 2 b, 3 a, 4 c
PUR) 1 d, 2 a, 3 b, 4 c
TEAL) 1 d, 2 c, 3 b, 4 a
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Peer Instruction: Match the Phrase
Match the memory hierarchy element on the left
with the closest phrase on the right:
1. L1 cache
a. A cache for page table entries
2. L2 cache
b. A cache for a main memory
3. Main memory c. A cache for disks
4. TLB
d. A cache for a cache
A) 1 a, 2 b, 3 c, 4 d
E) 1 b, 2 d, 3 c, 4 a
B) 1 a, 2 b, 3 d, 4 c
C) 1 b, 2 d, 3 a, 4 c
F) 1 d, 2 b, 3 a, 4 c
G) 1 d, 2 a, 3 b, 4 c
H) 1 d, 2 c, 3 b, 4 a
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Peer Instruction: True or False
A program tries to load a word X that causes a TLB
miss but not a page fault. Which are True or False:
1. A TLB miss means that the page table does not
contain a valid mapping for virtual page
corresponding to the address X
2. There is no need to look up in the page table
because there is no page fault
3. The word that the program is trying to load is
present in physical memory.
RED) 1 F, 2 F, 3 F
ORG) 1 F, 2 F, 3 T
GRN) 1 F, 2 T, 3 F
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PNK) 1 T, 2 F, 3 F
BLU) 1 T, 2 F, 3 T
PUR) 1 T, 2 T, 3 F
Spring 2011 -- Lecture #24
TEL) 1 T, 2 T, 3 T
60
Peer Instruction: True or False
A program tries to load a word X that causes a TLB
miss but not a page fault or protection violations.
Which are True or False:
1. A TLB miss means that the page table does not
contain a valid mapping for virtual page
corresponding to the address X
2. There is no need to look up the page table because
there is no page fault
3. The word that the program is trying to load is
present in physical memory.
A) 1 F, 2 F, 3 F
B) 1 F, 2 F, 3 T
C) 1 F, 2 T, 3 F
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E) 1 T, 2 F, 3 F
F) 1 T, 2 F, 3 T
G) 1 T, 2 T, 3 F
Spring 2011 -- Lecture #24
H) 1 T, 2 T, 3 T
61
Peer Instruction: True or False
TLBs entries have valid bits and dirty bits. Data caches have them also.
A. The valid bit means the same in both: if valid = 0, it must miss in both
TLBs and Caches.
B. The valid bit has different meanings. For caches, it means this entry is
valid if the address requested matches the tag. For TLBs, it determines
whether there is a page fault (valid=0) or not (valid=1).
C. The dirty bit means the same in both: the data in this block in the TLB or
Cache has been changed.
D. The dirty bit has different meanings. For caches, it means the data block
has been changed. For TLBs, it means that the page corresponding to this
TLB entry has been changed.
Red) 1 F, 2 T, 3 F, 4 T
Org) 1 F, 2 T, 3 T, 4 F
Grn) 1 T, 2 F, 3 F, 4 T
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Spring 2011 -- Lecture #24
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Peer Instruction: True or False
TLBs entries have valid bits and dirty bits. Data caches have them also.
A. The valid bit means the same in both: if valid = 0, it must miss in both
TLBs and Caches.
B. The valid bit has different meanings. For caches, it means this entry is
valid if the address requested matches the tag. For TLBs, it determines
whether there is a page fault (valid=0) or not (valid=1).
C. The dirty bit means the same in both: the data in this block in the TLB or
Cache has been changed.
D. The dirty bit has different meanings. For caches, it means the data block
has been changed. For TLBs, it means that the page corresponding to this
TLB entry has been changed.
A) 1 F, 2 T, 3 F, 4 T
B) 1 F, 2 T, 3 T, 4 F
C) 1 T, 2 F, 3 F, 4 T
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63