Transcript Virtual Memory - University of Waikato

Virtual Memory
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main memory can act as a cache for
secondary storage
motivation:
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Allow programs to use more memory that there is
available
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transparent to programmer
c.f. overlays
Allow multiple programs concurrently
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non-active part of of programs reside in secondary
storage
active portions of many programs reside in memory
active portion of current program in cache
Virtual Memory
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With multiple programs sharing memory have
to deal with:
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program relocation
protection
Give each program (process) it own (virtual)
address space
When program accesses memory
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translate virtual address to physical address
Virtual Memory
V ir t u a l a d d r e s s e s
P h y s ic a l a d d re s s e s
A d d r e s s tr a n s la tio n
D is k a d d r e s s e s
Definitions
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main concepts similar to caches
however different terminology used
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virtual memory block => page
virtual memory miss => page fault
Address Translation
Virtual address
15 14 13 12
31 30 29 28 27
11 10 9 8
3210
Page offset
Virtual page number
Translation
29 28 27
15 14 13 12
11 10 9 8
Physical page number
Physical address
Page offset
3210
Design Choices
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Page faults : when a page not in memory
then have to fetch from disk
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can take millions of cycles
Minimise miss penalty:
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make pages fairly large (4KB to 64KB)
reduce page fault rate:
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Use LRU replacement
High levels of associatively
make caches write-back
Placing/Finding a page
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Want Full associatively
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impractical to search all pages in memory
Use a page table to map virtual addresses to
physical addresses
Each program has its own page table
Page tables reside in memory
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reads/writes to main mem require twoo accesses:
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one to get page table entry
one to perform data transfer
Page Tables
Virtual page
number
Page table
Physical page or
disk address
Valid
Physical memory
1
1
1
1
0
1
1
0
1
1
0
1
Disk storage
Page Tables
Page table register
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Base address of
current page table
held in the page table
register
A programs state
defined by its
Virtual address
31 30 29 28 27
15 14 13 12 11 10 9 8
Virtual page number
Page offset
20
Valid
3 2 1 0
12
Physical page number
Page table
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PC
Registers
Page table
18
If 0 then page is not
present in memory
29 28 27
15 14 13 12 11 10 9 8
Physical page number
Physical address
Page offset
3 2 1 0
TLBs
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Translation-lookaside Buffer
cache of page table mappings
Typical values for a TLB might be:
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TLB size 32 – 4096 entries
Block Size: 1 – 2 page table entries
Hit time: 0.5 – 1 clock cycles
Miss penalty: 10 – 30 clock cycles
Miss rate: 0.01 – 1%
TLBs
Virtual page
number
TLB
Valid
Tag
Physical page
address
1
1
Physical memory
1
1
0
1
Page table
Physical page
Valid or disk address
1
1
1
1
0
1
1
0
1
1
0
1
Disk storage
TLBs and caches
Virtual address
TLB access
TLB miss
exception
No
Yes
TLB hit?
Physical address
No
Yes
Write?
Try to read data
from cache
No
Write protection
exception
Cache miss stall
No
Cache hit?
Yes
Deliver data
to the CPU
Write access
bit on?
Yes
Write data into cache,
update the tag, and put
the data and the address
into the write buffer
Virtual Memory Protection
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If a physical page is not pointed to from the
page table then it can not be accessed
Need to prevent a process from changing its
own page table
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user and supervisor modes
write protect bit to stop writes to the page table
Mechanism to allow swaps between user and
supervisor mode and vice versa
Modern Systems
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Very complicated memory systems:
Characteristic
Virtual address
Physical address
Page size
TLB organization
Intel Pentium Pro
32 bits
32 bits
4 KB, 4 MB
A TLB for instructions and a TLB for data
Both four-way set associative
Pseudo-LRU replacement
Instruction TLB: 32 entries
Data TLB: 64 entries
TLB misses handled in hardware
Characteristic
Cache organization
Cache size
Cache associativity
Replacement
Block size
Write policy
PowerPC 604
52 bits
32 bits
4 KB, selectable, and 256 MB
A TLB for instructions and a TLB for data
Both two-way set associative
LRU replacement
Instruction TLB: 128 entries
Data TLB: 128 entries
TLB misses handled in hardware
Intel Pentium Pro
Split instruction and data caches
8 KB each for instructions/data
Four-way set associative
Approximated LRU replacement
32 bytes
Write-back
PowerPC 604
Split intruction and data caches
16 KB each for instructions/data
Four-way set associative
LRU replacement
32 bytes
Write-back or write-through