Transcript Embedded System for Brushless Motor Control in Space Applications *G. C. Caprini, #F.

Embedded System for Brushless Motor Control in Space Applications
*G.
C. Caprini, #F. Innocenti, L. Fanucci, #S. Ricci,
#G. Taraschi, P. Terreni, M. Tonarelli, #L. Tosi
*Galileo
Avionica, Campi Bisenzio (FI), Italy
#Cesvit Microelettronica, Prato, Italy
Dept. of Information Engineering, University of Pisa, Pisa, Italy
AMBRA (ASIC for BRushless Motor control in space Applications) is a Multi Chip Module (MCM) device designed for high performance synchronous brushless motor control in space applications. Brushless motors are used in space applications for their simple and robust construction, high power output to weight ratio, low inertia
and optimal performances at high and low speed. Typical applications are scan mirror, thrust vector control actuators, fuel valve control actuators, solar array deployment, control moment gyroscopes, high and low RPM applications, light weight applications and low thermal emission applications. Motor control is achieved through a
DSP-based fully digital ASIC architecture. This solution provides, with respect to typical mixed analog-digital control systems, higher flexibility, cost reduction, drift elimination and greater radiation robustness which are highly required features in space systems.
System Overview
Hardware
VDC
Position
command
generation
Motor
Current/
Torque
control
Cascaded position and
speed control
PWM
generator
3-phase
Inverter
speed
position
position
Comm. interface
TX
Motor
current
aquisition
UART 1
RX
TX
ia
Motor
current
signal
conditioning
ib
UART 2
RX
SOUT
High speed
speed
Serial
Serial port
port
SIN
M
A.M.BR.A.
Position
and speed
extraction
Sensor
signal
aquisition
Position
sensor signal
conditioning
Sensor
signals
T
AMBRA is a MCM system made up of a digital ASIC, two analog to digital converters, a four double channels
multiplexer and a ROM.
AMBRA system communicates with external devices by an analog interface and some digital ones:
• encoder interface
• serial interface
• inverter bridge interface
• input/output digital interface
System block diagram includes the required motor control external components: brushless motor, position
transducer, position sensor signal conditioning, current signal conditioning and 3-phase inverter.
The fully digital ASIC carries out all the functions for brushless motor control, the system acquires two of the three
motor currents and relative position transducer signals and it provides PWM (Pulse Width Modulation) signals to
drive the 3-phase inverter to reach the final motor position.
Two 12 bit - 10 MSPS A/D converters are required to simultaneously sample a couple of homogenous signals
coming from motor current and position sensor.
Algorithms are partitioned between hardware and firmware (DSP) implementations according to the required speed
performances, their criticality and flexibility (for instance to cope with possible new system requirements).
A.M.BR.A. system and peripheral devices
Position transducer interface (incremental encoder)
Position and speed extraction
Brushless motor current/torque FOC
High resolution PWM signals generator
Programmable digital I/O communication interface
Serial Interface
PID controller
System requirements:
• 2-3 kHz current control band
• 21.8 kHz FOC (Field Oriented Control) work frequency
• 3.6 kHz position and speed loop work frequency
• 100 ns analog to digital time conversion
• 12 bit analog to digital resolution.
Algorithms
RESET CLK
APC
KFA
s2
1/s
+
+
-
K PI
+
PE
KPP
s
PF
+
+
+
+
+
Isqref
+
KPD
PID controller
HARDWARE
sin
ADC
Resolver
x8
cos
sin
Resolver
x1
cos
Filtering and
Undersampling
ADC
Angle
calculation
ADC
Octant
Calculation
Octant
integration
ADC
Position computation algorithm
1
0.5
Program
Memory
Algorithms performances, depending
on resolver kind, with multispeed x1
x8 resolver:
accuracy : 0.10625 millidegrees
resolution < 0.125 millidegrees
precision : 0.0075 millidegrees
Data
Memory
I/O
Two RAM data memories 256x16 and a
RAM program memory 2048x16;
FOC (Field Oriented Control) equipment
unit implements direct and inverse Clarke &
Park transformation for PID calculation;
AD interface is engaged in reading data
from AD converter, controlling ADC and
data compensation;
Timing Unit produces all timing references
necessary for AMBRA system operation,
(resolver, A/D acquisition, Clarke & Park
conversion and PI calculation);
Resolver
OUT
Timing
unit
16 bit - fixed point DSP macro cell
characterized by 10 MIPS computational
power;
Interrupt
controller
Register Block interfaces the DSP core with
the rest of the circuit; we have three kind of
registers: Setup, Operational and Special;
FOC
We have three kind of module:
1. One shot : executed once or in special situations
2. Low priority : performing not critical functions
3. High priority : performing functions of
vital
importance for system activity.
For each group the modules are executed in
circular priority.
The modules are divided into two different cycles:
1. PWM cycle : FOC calculates signals for PWM
and MOS commands are generated .
2. Resolver cycle : resolver excitation waveform
period it contains an integer number of PWM
cycles.
Developed tasks :
1. Filter
2. Position calculation
3. PID controller
4. Trajectory calculation
5. Serial communication
synchronization
to hardware
PWM unit generates the signals for driving
the MOSFET gates of the inverter bridge.
ASIC
ADC
System
8 IN
UART
High
speed
Serial port
Vref OUT
PWM
generator
Encoder
Interface
6 OUT
The Encoder block interfaces an external
incremental encoder
TRIG
To improve transportability all the hardware
blocks have been described in technologyindependent VHDL (Very high-speed
integrated circuits Hardware Description
Language) code.
A.M.BR.A. block diagram
PORTOUT
EXT_INT
Timing
Block
DATA
Memory
Block
DSP
Task
TASK manager
one
shot
high
priority
low
priority
one
shot
high
priority
low
priority
high
priority
low
priority
Firmware modules scheduling
PORTIN
WAVE
MCM implementation
ADDRESS
These algorithms are managed as task
in a real-time operative system.
Several algorithms, not concurring to
achieve request performances, are
implemented in firmware (serial
communication, tasks management
algorithms etc.)
Register
Block
SER_IN
SER_OUT
IA
IB
IS
IZ
Serial
Interface
The ASIC design was finalized by
means of logic synthesis for the 0.35
µm CMOS Austriamicrosystems
technology.
The rationale behind this choice is:
to allow technology access through
reduced price multi-project wafer and
to reduce risks in case of technology
retargeting to a radiation tolerant
technology (0.35 µm CMOS provided
by ATMEL (MH1RT)).
FOC
Space
Vector
Encoder
Interface
CHA
CHB
CHANNEL
Sampling scheme
0
-0.5
CPU
ASIC circuit includes the following devices:
Rotor position elaboration, position PID control
function and FOC reference current generation are
implemented in firmware by the selected DSP core.
To ease maintenance each functionality has been
derived as independent module.
We can modify, activate or deactivate modules to
change or to improve system functionality and
performances.
A task manager oversees all module operations in a
preemptive mode.
Space Vector is in charge of controlling the
generation of the PWM channels;
To reduce errors we use a not
uniform 16 points correlation with
3,5 bit ENOB gain.
Calculated
Position
16 IN
16 OUT
To ease ASIC testability a fully synchronous
approach was pursued.
Serial Interface block, used for debug,
performance evaluation and program
memory boot, includes an asynchronous
UART in addition to the DSP internal
synchronous serial interface;
INT
MCM
Algorithms considered:
1. PID algorithm to increase dynamic
performance in position control.
2. Trajectory generation to control
brushless rotor movement.
3. Position computation to calculate
rotor position from resolver data.
POSITION CALCULATION
Filtering and
Undersampling
AMBRA implements a motor
position control based on two nested
closed loops.
The inner loop is in charge of current
and torque controls.
The external loop manages the motor
position and speed.
HW/SW
SW
HW
HW
HW
HW/SW
SW
The ASIC architecture was developed as a
trade-off between performance, complexity
and flexibility.
Firmware
PWM
AD
Interface
PWM A
PWM B
PWM C
ASIC architecture
Verification Approach
Before ASIC foundry run, the overall design has been verified through rapid prototyping on a customarily
designed breadboard.
-1
Breadboard components:
0
500
1000
1500
2000
• Xilinx XC2V4000 FPGA
• RS232 interface
• two A/D converters
• permanent magnet 3-phase motor with resolver
• 3 phase MOS bridge with relative driver
• analog interface modules
The AMBRA circuitry required 33% of the overall FPGA resources (13% due to the DSP core).
PMSM Motor
Position signals and motor current
conditioning
FPGA Board
Motor driver
ASIC layout
Final chip features:
• 144 Pads
- 67 inputs
- 47 outputs
- 30 power supply pads
• PAD limited
• Area : 19.901 mm2
• Clock frequency : 20 MHz
• Power consumption : 226.3 mW @
3.3 V
• Fault coverage greater than 97%
Several test have been implemented: system test of PI control current evaluating step response
 rise time : 90 µs
 settling time : 700 µs
 current band : 2.8 kHz
With a multi-speed (x1 x8) resolver the AMBRA position precision amounts to 19 bit.
MCM is built on 1.6 FR4 substrate with tracks and isolations of 100 µm.
MCM components :
Rad-hard 8Kx8 PROM
Analog multiplexer
space qualified
4:1 - 2 channels
28 pin flatpack - die
space qualified - die
Proper test vectors have been developed to verify the functionality of the prototyped system.
(i) test program loading into DSP program memory;
(ii) DSP initialization of ASIC registers;
(iii) particular position and current values simulation;
(iv) DSP position computation;
(v) full FOC cycle execution;
(vi) DSP reading of FOC cycle results;
(vi) computed values verification.
Summarizing, the main advantages of the presented AMBRA motor control system are:
• great reduction in the number of devices
• size and cost reduction
• radiation/temperature/aging robustness
• increase in the overall reliability due to the fully digital approach
• higher system flexibility
• reduced design time/efforts
• system re-use in many other applications based on actual position sensor (sine/cosine encoder)
Caprini
A/D converter
Breadboard
12-Bit A/D converter
10 MSPS (tconv < 50 ns)
space qualified
28 pin DIL - die
P151/MAPLD 2004