MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University of.
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MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University of California, Santa Barbara [email protected] 805-893-3244, 805-893-5705 fax Scope of Presentation Topic of discussion is channel materials for CMOS ...the potential use of III-V materials ...and their advantages and limitations To understand this, we must examine in some detail MOSFET scaling limits th Zero -Order MOSFET Operation Bipolar Transistor ~ MOSFET Below Threshold Vbe Vce Ic Because emit t erenergy dist ribut ion is t hermal(exponental) i I c exp(qVbe / kT ) Almostall elect ronsreachingbase pass t hroughit I c varieslit t lewit h collect orvolt age Field-Effect Transistor Operation source gate drain Positive Gate Voltage → reduced energy barrier → increased drain current FETs: Computing Their Characteristics Cgs ~ A / D Id Q / Cd ch where Lg / velectron Q CgsVgs Cd chVds I d gm Vgs Gds Vds where gm Cgs / and Ggd Cd ch / FET Characteristics ID increasing VGS Cgs ~ A / D Cd ch VDS I d gm Vgs Gds Vds gm Cgs / Ggd Cd ch / Lg / velectron FET Subthreshold Characteristics Vgate Vox Vchannel ( qns ) Cox ( qns ) kT qns q Stronggate drive : channelcharge varieslinearly withVgs Weak gate drive : channelcharge variesexponentially withVgs Classical Long-Channel MOSFET Theory Assumptions : 1) Moderatelateralfield E in channel. n( x ) 2) T ransportmodeledby drift/diffusion J qn n( x ) E qDn x 3) Exit velocity at end of pinched- off channel: vexit vthermal kT / m* Classic Long-Channel MOSFET Theory constant-current mobility-limited Ohmic ID Id increasing VGS velocity-limited Vgs Vth For drain voltageslarger than saturation: VDS mobility limitedcurrent I D , coxWg (Vgs Vth ) / 2 Lg 2 velocity limitedcurrent I D,v coxWg vexit (Vgs Vth ) Generalized Expression 2 ID ID I I D ,v D , 1 Classic Long-Channel FET : Far Above Threshold Id V Vth Vgs I D coxWg vexit (Vgs Vth V ) for (Vgs Vth ) / V 1 where V vexitLg / Exponential, Square-Law, Linear FET Characteristics Relevance of DC Parameters Digital circuit speed largely controlled by on-state current Standby power consumption controlled by off-state current Dynamic power consumption controlled by supply Voltage → Examine VLSI Power & Delay Relationships th Zero -Order VLSI Performance Analysis CMOS Power Dissipation & Gate Delay CPFET Vdd I on Gate delay gate CtotalVdd / 2 I on (Cwire C NFET CPFET )Vdd / 2 I on wiring capacitance usually dominates Cwire Dynamicdower dissipation : CNFET Off statecurrent Pdynamic CtotalVdd2 frequency (switchingprobability) 2 I off Vdd I off / I on exp( qVth / nkT ) Static Dissipat ion Pstatic I off Vdd Tradeoffbetween staticand dynamicdissipation : Pdynamic ~ CwireVdd2 f p Pstatic ~ Vdd IoneqVth / kT Why Large Current Density is Needed FET with n 6 fingers, each of width Wg totalwidth nWg G S D S D S D Wg G T odrive Cwire at delay , requires current I d CwireVdd / 2 . I on If I d /Wg is small, large FET sare needed. Large FET s long wires large Cwire . CPFET Vdd Cwire CNFET S Device Requirements High on-state current per unit gate width Low off-state current→ subthreshold slope Low device capacitance; but only to point where wires dominate Low supply voltage: probably 0.5 to 0.7 V What Are Our Goals ? Low off-state current (10 nA/m) for low static dissipation → good subthreshold slope → minimum Lg / Tox low gate tunneling, low band-band tunneling Low delay CFET V/I d in gates where transistor capacitances dominate. ~1 fF/m parasitic capacitances → low Cgs is desirable, but high Id is imperative Low delay Cwire V/Id in gates where wiring capacitances dominate. large FET footprint → long wires between gates → need high Id / Wg ; target ~5 mA/m @ V= 0.7V target ~ 3 mA/m @ V= 0.5V Improving FETs by Scaling Simple FET Scaling Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays → keep constant all resistances, voltages, currents All lengths, widths, thicknesses reduced 2:1 S/D contact resistivity reduced 4:1 Cgd / Wg ~ gm / Wg ~ v / Tox Cgs / Wg ~ Lg / Tox Cgs, f / Wg ~ Csb / Wg ~ Lc / Tsub If Tox cannot scale with gate length, Cparasitic / Cgs increases, gm / Wg does not increase hence Cparasitic /gm does not scale FET scaling: Output Conductance & DIBL ( Cgs expressionneglectsD.O.S. effects) Cgs ~ Wg Lg / Tox Id Q / Cd ch ~ Wg where Q CgsVgs Cd chVds transconductance output conductance → Keep Lg / Tox constant as we scale Lg FET Scaling Laws LG gate width WG Changes required to double transistor bandwidth: parameter gate length gate dielectric capacitance density gate dielectric equivalent thickness channel electron density source & drain contact resistance current density (mA/m) change decrease 2:1 increase 2:1 decrease 2:1 increase 2:1 decrease 4:1 increase 2:1 nm Transistors: it's all about the interfaces Metal-semiconductor interfaces (Ohmic contacts): very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density Transistor & IC thermal resistivity. FET Scaling Laws LG gate width WG Changes required to double transistor bandwidth: parameter gate length gate dielectric capacitance density gate dielectric equivalent thickness channel electron density source & drain contact resistance current density (mA/m) change decrease 2:1 increase 2:1 decrease 2:1 increase 2:1 decrease 4:1 increase 2:1 What do we do if gate dielectric cannot be further scaled ? Why Consider MOSFETs with III-V Channels ? If FETs cannot be further scaled, instead increase electron velocity: Id / Wg = qnsv Id / Qtransit = v / Lg III-V materials → lower m*→ higher velocity ( need > 1000 cm2 /V-s mobility) Candidate materials (?) InxGa1-xAs, InP, InAs ( InSb, GaAs) Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current III-V CMOS: The Benefit Is Low Mass, Not High Mobility Simple drift - diffusion theory,nondegenerate,far above threshold: I D coxWg vinjection(Vgs Vth V ) where vinjection ~ vthermal (kT / m* )1/2 Id V vinjectionLg / Ensure thatV (Vgs Vth ) ~ 700 mV Vth Vgs low effective mass → high currents mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg III-V MOSFETs for VLSI What is it ? MOSFET with an InGaAs channel Why do it ? low electron effective mass→ higher electron velocity more current, less charge at a given insulator thickness & gate length very low access resistance What are the problems ? low electron effective mass→ constraints on scaling ! must grow high-K on InGaAs, must grow InGaAs on Si Device characteristics must be considered in more detail III-V MOSFET Characteristics Low Effective Mass Impairs Vertical Scaling Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering. 2 . Energy of Lth well state L2 / m*Twell For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Only one vertical state in well. Minimum ~ 5 nm well thickness. → Hard to scale below 22 nm Lg. Semiconductor (Wavefunction Depth) Capacitance Bound stateenergy 2 Ewell L2 / m*Twell . T 3 2 Energy(eV) Semiconductor capacitance csemiconductor / Tsemi semi 1 0 -1 -2 -3 -4 0 50 100 150 Y (Ang.) 200 250 Density-Of-States Capacitance E f Ewell ns /(nm* / 2 ) (bidirectional motion) V f Vwell s / cdos where cdos q2nm* / 2 and n is the # of band minima Two implications: - With Ns >1013/cm2, electrons populate satellite valleys Fischetti et al, IEDM2007 - Transconductance dominated by finite state density Solomon & Laux , IEDM2001 Current Including Density of States, Wavefunction Depth Simple drift - diffusion theory,nondegenerate,far above threshold: I D ceqWg vthermal (Vgs Vth V ) where1/ceq 1/cox 1/csemiconductor 1/cDOS Id Vth Vgs ...but with III-V materials, we must also consider degenerate carrier concentrations. Current of Degenerate & Ballistic FET ( Lundstrom, Natori,Laux, Solomon,Fischetti, Asbeck,...) Densityof states: dNs / dE f n m* / 2 2 (unidirectional mot ion) Highly degenerate: elect rondensity: ns n ( m* / 2 2 )(E f Ec ), Fermi velocity: v f 2( E f Ec ) / m* , 1/ 2 Mean elect ronvelocity: v ( 4 / 3 )v f . Current density: 2 q n m J qns v 2 3 3/ 2 5/ 2 1/ 2 mA m* n 84 m m0 ( E * 1/ 2 Ec ) / q 3/ 2 f 2 E f Ec 1 eV 3/ 2 2D vs. 1D Field-Effect Transistors in Ballistic Limit Drain Id 2D - FET ; InGaAs channel(m*/m0 0.04) gate E 1/ 2 Wg gate mA m* E f Ec mA E f Ec J 84 17 m m0 1 eV m 1 eV for 0.3eV Fermilevel shift in semiconductor. 3/ 2 3/ 2 Lg Source Drains Id Array of 1D - FET s;5 nm InGaAs wells @ 6 nm pit ch gate E Ewell Wg gate Lg Sources 2 2 0.37 eV, g m ,well 2 q 2 / h 78S 2 2m * Twell mA 78 A E f Ec mA E f Ec J 13 3 . 9 m 6 nm 1 eV m 1 eV for 0.3eV Fermilevel shift in semiconduct or 2.8 mA m 2D FET vs. Carbon Nanotube FET Drain Id gate 2D - FET ; InGaAs channel( m * /m0 0.04) mA E f Ec mA J 17 , 2.8 m m 1 eV for 0.3eV Fermilevel shift in semiconductor. 3/ 2 E Wg gate Lg Source Drains Array of carbon nanotubes, 5 nm pitch gate g m ,tube 2 q 2 / h 78S Wg Lg Sources mA E f Ec mA 78 A E f Ec J 15 . 5 4 . 7 m 1 eV m 5 nm 1 eV for 0.3eV Fermilevel shift in semiconductor Ballistic/Degenerate Drive Current vs. Gate Voltage More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007 Drive Current in the Ballistic & Degenerate Limits mA Vgs Vth J K 84 m 1 V 0.25 3/ 2 , where K 0.7 nm, n=6 K 1/ 2 * dos ,o / cox ) n ( m / mo ) 3/ 2 0.4 nm, n=6 Error bars on Si data points correct for (Ef-Ec)>> kT approximation 0.2 0.15 1 (c n m* mo n = # band minima cdos,o = density of states capacitance for m*=mo & n=1 0.8 nm, n=1 0.1 1.0 nm, n=1 0.05 EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0 0.01 0.1 m*/m 1 o High Drive Current Requires Low Access Resistance sidewall gate dielectric metal gate source contact N+ source drain contact quantum well / channel N+ drain barrier substrate For 10% impacton drive current, I D RS /(VDD Vth ) 0.1 T arget I D / Wg ~ 1.5 mA/m @ (VDD Vth ) 0.3 V T arget I D / Wg ~ 3 mA/m @ (VDD Vth ) 0.5 V RsWg 15 20 m Materials Selection; What channel material should we use ? Common III-V Semiconductors B. Brar 450 1350 AlSb 200 250 1550 InSb 220 500 AlAs GaSb 2170 770 1900 GaAs 200 1420 InAlAs InGaAs 1460 760 InAs 360 InGaP 450 InP 1350 150 200 170 550 200 6.48 A lattice constant 6.48 A lattice constant 5.65 A lattice constant; grown on GaAs 5.87 A lattice constant; grown on InP Semiconductor & Metal Band Alignments M. Wistey Materials of Interest Source: Ioffe Institute http://www.ioffe.rssi.ru/SVA/NSM/Semicond rough #s only material Si Ge GaAs InP In0.53Ga0.47As InAs n 6 6 1 1 1 1 m*/m0 0.98 ml 1.6 ml 0.063 0.19 mt 0.08 mt 0.08 0.04 0.023 G-(L/X) separation, eV -- -- 0.29 ~0.5 0.5 0.73 bandgap, eV 1.12 0.66 1.42 1.34 0.74 0.35 mobility, cm2/V-s 1000 2000 5000 3000 10,000 25,000 high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7 ??? Drive Current in the Ballistic & Degenerate Limits mA Vgs Vth J K 84 m 1 V 0.25 3/ 2 , where K 0.7 nm, n=6 1 (c n m* mo K 1/ 2 * dos ,o / cox ) n ( m / mo ) 3/ 2 0.4 nm, n=6 Error bars on Si data points correct for (Ef-Ec)>> kT approximation 0.2 0.15 Ge 0.8 nm, n=1 InGaAs InP 0.1 Si n = # band minima cdos,o = density of states capacitance for m*=mo & n=1 1.0 nm, n=1 0.05 EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0 0.01 0.1 m*/m 1 o Intervalley Separation Intervalley separation sets: -high-field velocity through intervalley scattering -maximum electron density in channel without increased carrier effective mass Source: Ioffe Institute http://www.ioffe.rssi.ru/SVA/NSM/Semicond Choosing Channel Material: Other Considerations Ge: low bandgap GaAs: low intervalley separation InP: good intervalley separation Good contacts only via InGaAs→ band offsets moderate mass→ better vertical scaling InGaAs good intervalley separation bandgap too low ? → quantization low mass→ high well energy→ poor vertical scaling InAs: good intervalley separation bandgap too low very low mass→ high well energy→ poor vertical scaling Non-Parabolic Bands Bands are ~ parabolic only for k near zero. At high energies, bands become nearly hyperbolic. Asypt oticgroup velocit y. Similar in most semiconduct ors. P arabolic- band FET expressions are generally pessimist ic. Non-Parabolic Bands T. Ishibashi, IEEE Transactions on Electron Devices, 48,11 , Nov. 2001, MOSFET Design Assuming In0.5Ga0.5As Channel Device Design / Fabrication Goals sidewall gate dielectric metal gate source contact N+ source drain contact quantum well / channel N+ drain barrier substrate Device gate overdrive drive current Ns 700 5 6*1012 500 3 4*1012 300 1.4 2.5*1012 mV mA/m 1/cm2 Dielectric: EOT 0.6 nm target, ~1.5 nm short term Channel : 5 nm thick > 1000 cm2/V-s @ 5 nm, 6*1012 /cm2 S/D access resistance: 20 -m resistivity→ 0.5 -m2 contacts , ~2*1013 /cm2 , ~4*1019 /cm3 , 5 nm depth Target Device Parameters sidewall gate dielectric metal gate source contact N+ source drain contact quantum well / channel N+ drain barrier substrate well : ns ~ 5 1012 / cm2 , 5 nm thick 5 1019 / cm3 , 5 nm thick ns 2.5 1013 / cm2 (0.25 m2 ) /(25 nm wide contact) 10 m Device Structure & Process Flow Device Fabrication: Goals & Challenges III-V HEMTs are built like this→ Source Gate Drain K Shinohara ....and most III-V MOSFETs are built like this→ Device Fabrication: Goals & Challenges Yet, we are developing, at great effort, a structure like this → N+ source regrowth r TiW r InGaAs well InP well barrier Why ? Source Gate K Shinohara Drain N+ drain regrowth Why not just build HEMTs ? Gate Barrier is Low ! Gate barrier is low: ~0.6 eV Source Gate Drain K Shinohara Tunneling through barrier → sets minimum thickness Emission over barrier → limits 2D carrier density Ec EF Ec EF Ewell-G Ewell-G At Ns 1013 / cm2 , (E f Ec ) ~ 0.6 eV Why not just build HEMTs ? Gate barrier also lies under source / drain contacts Source Gate Drain N+ layer widegap barrier layer K Shinohara low leakage: need high barrier under gate low resistance: need low barrier under contacts Ec EF Ec EF Ewell-G N+ cap layer Ewell-G The Structure We Need -- is Much Like a Si MOSFET sidewall gate dielectric metal gate source contact N+ source drain contact N+ drain quantum well / channel barrier substrate no gate barrier under S/D contacts high-K gate barrier Overlap between gate and N+ source/drain How do we make this device ? S/D Regrowth Process Flow Regrown S/D FETs: Versions regrowth under sidewalls planar regrowth need thin sidewalls (now ~20-30 nm) ..or doping under sidewalls Wistey et al 2008 MBE conference S/D Regrowth by Migration-Enhanced Epitaxy Wistey et al 2008 MBE conference MBE growth is line-of-sight → gaps in regrowth near gate edges MEE provides surface migration during regrowth→ eliminates gaps SEM Cross Section SEM Side View (Oblique) Top of gate SiO2 dummy gate InGaAs Regrowth Original Interface Side of gate InGaAs Regrowth SEM: Greg Burek No gaps Smooth surfaces. SiO2 dummy gate SEM: Uttam Singisetti High Si activation (4x1019 cm-3). Quasi-selective: no growth on sidewalls 6 Self-Aligned Planar III-V MOSFETs by Regrowth N+ InGaAs regrowth, Mo contact metal Mo contact metal gate Wistey Singisetti Burek Lee Self-Aligned Planar III-V MOSFETs by Regrowth Wistey Singisetti Burek Lee Regrown S/D FETs: Images Regrown S/D FETs: Images III-V MOS InGaAs / InP MOSFETs: Why and Why Not low m*/m0 → high vcarrier → more current low m*/m0 → low density of states → less current 0.25 ballistic / degenerate calculation 0.7 nm, n=6 0.4 nm, n=6 0.2 Error bars on Si data points correct for (EfEc)>> kT approximation K 0.15 n = # band minima cdos,o = density of states capacitance for m*=mo & n=1 mA Vgs Vth J K 84 m 1 V 3/ 2 , n m* mo 1/ 2 0.8 nm, n=1 where K 0.1 1.0 nm, n=1 0.05 cdos ,o m* 1 n mo cox EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0 0.01 0.1 m*/m 1 o Low m* impairs vertical (hence Lg ) scaling ; InGaAs no good below 22-nm. InGaAs allows very low access resistance Si wins if high-K scales below 0.6 nm EOT; otherwise, III-V has a chance 3/ 2 InGaAs/InP Channel MOSFETs for VLSI Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm Devices cannot scale much below 22 nm Lg→ limits IC density Little CV/I benefit in gate lengths below 22 nm Lg Need device structure with very low access resistance radical re-work of device structure & process flow Gate dielectrics, III-V growth on Si: also under intensive development