CS61CL Machine Structures Lec 8 – State and Register Transfers David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

CS61CL Road Map

HLL Program Asm Lang. Pgm

foo.s

foo.c

Machine Lang. pgm

foo.o

foo.exe

Software Hardware 10/14/09 Instruction Set Architecture Machine Organization CS61CL F09 Instr. Set Proc.

I/O system Datapath & Control Digital Design Circuit Design Layout & fab

Semiconductor Materials

2

Review: Combinational Logic

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Any boolean function can be expressed as an acyclic connection of gates Often specified by a truth table k inputs outputs Combinational Logic 2 k

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Outputs are purely a function of the inputs

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no history, no state 10/14/09 CS61CL F09 3

Examples: Logical Operations A B A 31 B 31 A 30 B 30 C = A & B A 0 B 0 C A 31:0 B 31:0 A 31:0 B 31:0

°°°

C 31 C 30 A 31:0 B 31:0 C 0 A 31:0 C 31:0 C 31:0 CS61CL F09 C 31:0 C 31:0 4 10/14/09

Example: Multiplexor A B C = S ? A : B C = (S & A) | (~S & B) S C A 31:0 B 31:0 S C 31:0 CS61CL F09 10/14/09 5

Example: Adder A B Ci Co S A B Ci A B Ci A B Ci A B Ci Co S Co S Co S Co S A 31:0 B 31:0 C 31:0 CS61CL F09 10/14/09 6

Example: Arithmetic Logic Unit A 31:0 B 31:0 10/14/09 S 1:0 C 31:0 CS61CL F09 7

ALU 10/14/09 CS61CL F09 8

Element of Time

+3 V out

Propagation delay

0 T • •

Logical change is not instantaneous Broader digital design methodology has to make it appears as such

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Clocking, delay estimation, glitch avoidance 10/14/09 CS61CL F09 9

What makes Digital Systems tick?

Combinational Logic 10/14/09 clk time CS61CL F09 10

Administrative Issues

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HW 6 due tonight Project 2 dues Monday 10/26

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bimodal check-off testing tools available tomorrow they are really picky Project 1 grading almost done

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Friday HW 7 – discuss

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Midterm 2 on 11/9 as in original schedule

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11/11 is holiday CS61CL F09 10/14/09 11

A Bit of state: D-type edge-triggered flip-flop

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The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering).

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At all other times the output Q is independent of the input D (just stores previously sampled value).

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The input must be stable for a short time before the clock edge. 8/30/2007 12

Registers

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Collections of flip-flops with similar controls and logic

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Stored values somehow related (e.g., form binary value) Share clock, reset, and set lines Similar logic at each stage

OUT1 OUT2 OUT3 OUT4 "0" R S D Q R S D Q R S D Q R S D Q CLK IN1 IN2 IN3 IN4

13 9/18/07

r0 r1

° ° °

r31 PC lo hi What “registers” do we need?

0

Programmable storage

2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC • • •

“read” vs use the output “write” on the clock edge => Load Load Control CS61CL F09 10/14/09 14

Register with Load Control load clock R 31 1 0 R 0 10/14/09 CS61CL F09 15

Register File Din

Dsel

1 R0 R1 R2

°°°

R31 ld CS61CL F09 10/14/09

Asel Bsel

Bout Aout 16

Towards a Data Path

Asel Bsel Dsel ld aluOP °°°

10/14/09 CS61CL F09 17

Exercise a Data Path 10/14/09

Asel Bsel Dsel ld

2 4 2 1 7 10 13 3

°°°

13 3

aluOP

16 CS61CL F09 18

What about RAM - Randomly Accessed Memory?

RAM address data

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Like a HUGE register file

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dense, slower, low-cost storage cell (6T) fewer ports wider address lines accessed over a “bus” Bus: means of composition in hardware system

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logically related collection of wires interfacing one or more sources to one or more destinations 10/14/09 CS61CL F09 19

Recall: Instruction Cycle 000..0: n: main: 0B20:

°°°

FFF..F:

Instruction Fetch Decode Operand Execute Result Next

PC 40 61 101 + 9/16/09 UCB CS61CL F09 Lec 4 32 2 3 1 “add $1,$2,$3” 20

Register Transfers 10/14/09 CS61CL F09 21

Synchronous Circuit Design

clock input input CL reg CL reg output option feedback • •

Combinational Logic Blocks (CL)

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Acyclic

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no internal state (no feedback) output only a function of inputs Registers (reg)

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collections of flip-flops

output • •

clock

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distributed to all flip-flops ALL CYCLES GO THROUGH A REG!

10/14/09 CS61CL F09 22