Transcript Is Dual Gate Device Structure Better From a Thermal Perspective? D. Vasileska, K.

Is Dual Gate Device
Structure Better From a
Thermal Perspective?
D. Vasileska, K. Raleva and
S. M. Goodnick
Arizona State University
Tempe, AZ USA
Technology Trends and Device
Miniaturization Solutions
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
Why Heating Effects in Alternative
Device Geometries?
L~
300nm
dS
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
Complexity of the Problem:
Treatment of Phonons
1
- phonon mean free
length (=1-2nm)
0.8
High Electric Field
Molecular
Dynamics
Hot Electron Transport
~ 0.1ps
Optical Phonon
Emission
~ 10ps
~ 0.1ps
0.6
Acoustic Phonon
Emission
0.4
L-Phonon mean free path
(L=300nm)
Phonon Boltzmann
Transport Equation
Fourier Law
Classical SOI Structures
Superlattice
~ 10ps
0.2
Nanotubes
Heat Conduction
in Semiconductor
0
-9
10
-8
-7
10
10
Silicon layer thickness (m)
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
-6
10
ASU Solution

e
 

k+q k
k+q k
k k+q
k k+q
 Wa,q
 We,q
 Wa,q
 t  ve (k)   r  E  r    k  f   We,q


q

 (13a)

 

 g 
k+q k
k k+q

v
(
q
)


g

W

W


p
r
e
,q
a
,q
 t

 t 



 p p
k
J. Lai and A. Majumdar, “Concurent thermal
and electrical modeling of submicrometer
silicon devices”, J. Appl. Phys. , Vol. 79, 7353
(1996).
TLO 3nk B  Te  TL


t
2   e LO
 nm * vd2
 TLO  TA 
CLO


C

 , (14a)
LO 
2


e  LO

 LO  A 
 T  TA  3nk B  Te  TL 
T
C A A     k ATA   CLO  LO


 . (14b)
t

2

 LO  A 
 e L 
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
(13b)
Thermal EMC Device Simulator
Exchange of Variables
Initialize
Calculate Scattering Table
Ensemble Monte
Carlo Device
Simulator
Find electron position in a gr id:(i,j)
Find: TL(i,j)=T A(i,j) and TLO(i,j)
Free-flight scatter
Check contacts
Solve Poisson
Current Convergence
TA
TLO
n
vd
Te
Phonon Energy
Balance Equations
Solver
Select the scattering table with
“coordinates”: ( TL(i,j)=T LO(i,j))
Generate a random number and
choose the scattering mechanism
for a given electron energy
Solve Phonon
Energy Balance
Equations
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
The Role of Velocity Overshoot:
Less Current Degradation
5
2.5
Velocity (m/s)
2
2
Ids (mA/um)
1.5
isothermal
T=300K
1.5
x 10
Vds=1.2V
Vds=1.1V
Vds=1.0V
Vds=0.8V
Vds=0.6V
Vds=0.4V
1
0.5
0
source
isothermal
T=400K
1
0
0
0.2
0.4
0.6
0.8
Vds (V)
drain
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
-8
x (m)
x 10
25 nm Channel Length Device
thermal
simulations
0.5
channel
1
1.2
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
Longer Channel Devices Affected More
T=300 K on gate
T=400 K on gate
25 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
25 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
3
3
source contact
drain contact
8
400
source region
13
500
10
600
source contact
500
8
400
drain region
20
30
40
50
60
300
70
13
10
20
3
500
12
400
21
300
40
60
80
100
30
40
50
60
300
70
45 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
45 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
20
drain contact
Acoustic
Phonon
Temperature
120
3
500
12
21
400
20
40
60
80
100
300
120
60 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
60 nm FD SOI nMOSFET (Vgs=Vds=1.2V)
3
3
500
15
400
15
300
27
500
27
20
40
60
80
100
120
140
160
180
20
40
60
80
100
120
140
160
180
600
500
20
3
600
500
20
400
35
50
100
150
300
200
400
35
50
100
150
300
200
90 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
90 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
3
3
500
21
39
600
21
400
400
50
100
150
200
300
250
39
50
100
150
200
250
100 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
100 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
3
3
500
23
600
500
23
50
100
150
200
250
300
300
Hot-Spot
Moves Towards the
Channel for Larger
Devices
400
400
43
300
80 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
80 nm FD SOI nMOSFET (Vgs=Vds=1.5V)
3
400
43
50
100
150
200
250
300
300
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
Can We Further Minimize Lattice
Heating Problems in Nanodevices?
Drain (n+)
Source (n+)
BOX
Bottom
gate
OUR ALTERNATIVES:
Si substrate
Dual Gate Devices
0
335
330
2
y (nm)
325
4
320
source
drain
315
6
310
8
305
10
0
25
50
x (nm)
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
75
300
Double-Gate SOI:
From Electrical Perspective
Double-Gate SOI:
Top
+ Enhanced SCE scalability
S
Tsi, Ultrathin Body,
Fully
Depleted
BOX
D
Bottom
+ Lower junction capacitance
+ Light doping possible
+ Vt can be set by WF of metal
gate electrode
SUBSTRATE
+ ~2x drive current
- ~2x gate capacitance
- High Rseries,s/d  raised S/D
- Complex process
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
Double-Gate SOI:
From Thermal Perspective
Average acoustic and optical phonon temperature profile in the silicon layer
580
560
540
channel
source
drain
Temperature (K)
520
500
480
460

Higher Lattice
Temperature
optical phonon temperature profile
25nm dual-gate
FD SOI nMOSFET
25nm single-gate
FD SOI nMOSFET
440
420
400
380
0
Higher Number
of Carriers

More Velocity
Degradation
lattice temperature profile
10
20
30
40
50
along the channel (nm)
60
70
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
A Closer Look …
Single gate lattice
temperature profile
Lattice temperature profile for undoped, single-gate 25nm FD SOI MOSFET
500
4
480
10
18
x 10
Average electron velocity and energy for 25nm single-gate and dual-gate FD SOI nMOSFET
0.7
460
20
16
440
0.6
420
30
14
400
380
40
0.5
12
360
50
10
20
30
40
50
60
70
300
Lattice temperature profile for 25nm DG SOI MOSFET
550
X= 15
Y= 9
Level= 416.422
X= 68
Y= 6
Level= 560.9467
10
10
Energy (eV)
320
60
Velocity (m/s)
340
8
6
0.4
0.3
500
4
20
y (nm)
bottom gate
region
set to 300K
0.2
450
30
2
40
400
0
0.1
dual-gate
single-gate
50
350
-2
0
60
10
20
30
40
x (nm)
50
60
70
300
25
50
along the channel (nm)
75
0
0
25
50
along the channel (nm)
Dual gate lattice
temperature profile
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics
75
25nm FD SOI nMOSFET
Where Does the
Benefit of the DG
Structure Comes
From?
Type of
simulation
Gate
temperatur
e
Bottom of
the BOX
temperatur
e
Current
(mA/um)
Current
decrease
(%)
isothermal
300K
300K
1.9428
\
thermal
300K
300K
1.7644
9.18
thermal
400K
300K
1.6641
14.35
thermal
600K
300K
1.4995
22.82
25nm DG SOI nMOSFET
25nm DG SOI nMOSFET
(Vgate-top=Vgate-bottom=1.2V; Vdrain=1.2V; Vsource=0V; Vsubstrate=0V)
For almost the same
Current degradation
DG devices offer
1.5-1.7 times more
current
Type of
simulation
Top gate
temperature
Bottom gate
temperature
Bottom of
the BOX
temperature
Current
(mA/um)
Current
decrease
(%)
isothermal
300K
300K
300K
3.0682
\
thermal
300K
300K
300K
2.7882
9.13
thermal
400K
400K
300K
2.6274
14.37
thermal
600K
600K
300K
2.3153
24.54
Ira A. Fulton School of Engineering
ND=1019 cm-3; NA= 1018 cm-3
AINE – Arizona Institute
for Nanoelectronics
t =2nm; t =10nm; t =50nm
ox
si
BOX
What Needs to be Done in Terms of
Modeling Thermal Effects?


When the heat conduction is nonlocal, the transport is highly
nonequilibrium, the temperature used to represent the modeling results
is at best a measure of the local energy density, rather than their typical
thermodynamic meaning.
 On the other hand, in microelectronics, the device reliability is often
associated with the temperature through the Arrehnius law, which is
a manifestation of the Boltzmann distribution and is a result
obtained under the assumption of local equilibrium.
The simulations so far are based on either Monte Carlo methods or the
Boltzmann equation and take the various relaxation times as input
parameters. These parameters are subject to a wide range of
uncertainties.
 There is a clear need for more accurate information on the
relaxation times. Molecular dynamics simulation may be one way to
obtain them.
 Similarly, electron-phonon scattering processes also need further
consideration, particularly when electrons have very different
temperatures from that of phonons.
Ira A. Fulton School of Engineering
AINE – Arizona Institute for Nanoelectronics