Microprocessors Functions of 68HC11 Microprocessor Providing tuning and control signal for all elements of microcomputer Fetching instruction and data from memory Transferring data from memory Decoding.
Download ReportTranscript Microprocessors Functions of 68HC11 Microprocessor Providing tuning and control signal for all elements of microcomputer Fetching instruction and data from memory Transferring data from memory Decoding.
Slide 1
Microprocessors
Slide 2
Functions of 68HC11
Microprocessor
Providing tuning and control signal for all
elements of microcomputer
Fetching instruction and data from memory
Transferring data from memory
Decoding instruction
Performing arithmetic and logic operations called
for by instructions
Responding to I/O generated control signals
such as reset and interrupt
Slide 3
68 HC MPU
5 16 bit registers
2 8 bit accumulators
8 bit condition code registers
Control bus signals are expandable
Slide 4
Timing and control section
Control Bus signal
AS signal
E clock
Reset
Slide 5
Functions of reset
Fetches the content of ROM address FFFE
and loads into PCH
Fetches the content of ROM address FFFF
and load it into PC1 so that (PC) is now
2AC6
Begin fetching and executing instruction at
address 2AC6
Slide 6
Microprocessor common function
Initialize MPU registers
Initialize I/O device control registers
Perform test on system RAM
Check status of I/O devices
Send messages to output devices
Slide 7
Instruction register
When the MPU fetches an instruction word
from memory it sends to the IR
Slide 8
Program Counter (PC)
Contains in the memory address of the
next instruction code that the MPU is to
fetch.
Slide 9
Accumulator
Register that takes part in most of the
operations performed by the ALU
It is also the register in which the result
are being placed after most ALU
operations
The source of the operand and destination
of the result
Slide 10
Data Address Register
Memory address register
Address latching register
Used when executing ADD instruction
Slide 11
General Purpose register
GPR the accumulators can perform the
function of a general purpose register in
many programming situations.
Slide 12
Common GPR instruction access
codes
Load GP from memory [M] > [GP]
Store GP in memory [GP] > [M]
Transfer contents of one GP register to
another GP register : [GP1] > [GP2]
Increment GP by 1: [GP +1 ] > [GP]
Decrement GP by 1: [GP-1] > [GP]
Slide 13
Start
This set [GP] =
COUNT
1
Load [GP] with value = COUNT
Fron the memory
2
Program Loop
Instruction Sequence to be
Executed a number of times
= COUNT
3
Decrement [GP]
[GP -1] > [GP]
4
Is [GP] = 0?
5
Yes
Next portion of
program
If [GP]
not = 0
branch
back to 2
If [GP] =0 go
to the next
instruction in
sequence
Slide 14
Index register
68HC11 has two 16 bit index register
(index register Y and index register X)
Similar to general purpose register
Its operation is called index addressing
It holds address base
index register
C45016 for X and Y
Slide 15
Offset instruction illustration for
register X
Address
C000
Instruction
code
A6
C001
04
Mnemonic
Description
LDAA $04,X
Load
accumulator A
from address
[X]+04.
Effective Address = offset + [X]
= 04 + C450
= C454
Offset byte
Slide 16
Y register instruction illustration
Address
Instruction Mnemonic
code
Description
C000
18
Load
accumulator A
C001
LDAA $04,Y
A6
from address
[Y]+04.
04
Offset byte
Effective Address = offset + [Y]
= 04 + C450
= C454
Slide 17
Important process during the
operation
Accumulator A and B are cleared to zero before any ADD
operation occurs
Index register [X] is initially loaded with the number
2067
Accumulator B is initially loaded with 07 which the
number of memory locations to be added. ACCB is
being used to count down the number of times that
blocks 5-8 are executed
Blocks 5-8 are executed a total of seven times before
ACCB is decrement to 00 program goes to block 9 to
store the final sum in memory location 2068
The ADD operation (block 5) are executed using data
from different address each time starting with 2067 and
ending with 2061.this means the data is now loaded to
the accumulator
Slide 18
Start
1
Clear [ACCA]
2 Clear [ACCB]
3
Load [X] with Value 2067
4
Load [ACCB] with value 07
5
Add data stored at
address [X] +00 to [ACAA]
6
7
Decrement [X]
Decrement ACCB
8
No
Is [ACCB]=0?
9
Store [ACCA] in
memory
location 2068
10
HALT
Slide 19
Condition Code register
Consist of individual bits
Each bits is called Flags
This is the 68HC11code register
b7
b6
b5
b4
b3
b2
b1
b0
S
X
H
I
N
Z
V
C
Slide 20
Condition Code functions
C – Carry flag reflects the carry status of arithmetic
operation.
V – the overflow use to indicate overflow whenever
signed numbers are being added or subtracted
Z – zero flag is automatically set to 1
N – negative used to indicate any sign result of any
arithmetic data manipulation
I- interrupt mask flag is used to indicate effects on the
IRQ
H – Half carry flag is change only by addition instruction
X – X interrupt mask used to indicate not XIRQ
S – stop disable flag is used to prevent the stop
instruction
Slide 21
Conditional branching
It examine the value of the zero flag
If zero flag is = 0
The next instruction will be taken at a normal
sequence
If zero flag is = 1
The program will branch into new address for
the next instruction
If carry clear (BCC) or set booth will examine
the carry flag
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Two operands operators
Add
Subtract
Slide 28
Accumulator and memory
instructions
Slide 29
Load, Store and transfer instruction
Slide 30
Arithmetic operation instruction
Slide 31
Continuation..
Slide 32
Multiply and divide instruction
Slide 33
Logical operation instruction
Slide 34
Shift and rotate instructions
Slide 35
Stack and
index
register
instruction
Slide 36
Condition code register instruction
Slide 37
Slide 38
Branch
instructions
Slide 39
Microprocessors
Slide 2
Functions of 68HC11
Microprocessor
Providing tuning and control signal for all
elements of microcomputer
Fetching instruction and data from memory
Transferring data from memory
Decoding instruction
Performing arithmetic and logic operations called
for by instructions
Responding to I/O generated control signals
such as reset and interrupt
Slide 3
68 HC MPU
5 16 bit registers
2 8 bit accumulators
8 bit condition code registers
Control bus signals are expandable
Slide 4
Timing and control section
Control Bus signal
AS signal
E clock
Reset
Slide 5
Functions of reset
Fetches the content of ROM address FFFE
and loads into PCH
Fetches the content of ROM address FFFF
and load it into PC1 so that (PC) is now
2AC6
Begin fetching and executing instruction at
address 2AC6
Slide 6
Microprocessor common function
Initialize MPU registers
Initialize I/O device control registers
Perform test on system RAM
Check status of I/O devices
Send messages to output devices
Slide 7
Instruction register
When the MPU fetches an instruction word
from memory it sends to the IR
Slide 8
Program Counter (PC)
Contains in the memory address of the
next instruction code that the MPU is to
fetch.
Slide 9
Accumulator
Register that takes part in most of the
operations performed by the ALU
It is also the register in which the result
are being placed after most ALU
operations
The source of the operand and destination
of the result
Slide 10
Data Address Register
Memory address register
Address latching register
Used when executing ADD instruction
Slide 11
General Purpose register
GPR the accumulators can perform the
function of a general purpose register in
many programming situations.
Slide 12
Common GPR instruction access
codes
Load GP from memory [M] > [GP]
Store GP in memory [GP] > [M]
Transfer contents of one GP register to
another GP register : [GP1] > [GP2]
Increment GP by 1: [GP +1 ] > [GP]
Decrement GP by 1: [GP-1] > [GP]
Slide 13
Start
This set [GP] =
COUNT
1
Load [GP] with value = COUNT
Fron the memory
2
Program Loop
Instruction Sequence to be
Executed a number of times
= COUNT
3
Decrement [GP]
[GP -1] > [GP]
4
Is [GP] = 0?
5
Yes
Next portion of
program
If [GP]
not = 0
branch
back to 2
If [GP] =0 go
to the next
instruction in
sequence
Slide 14
Index register
68HC11 has two 16 bit index register
(index register Y and index register X)
Similar to general purpose register
Its operation is called index addressing
It holds address base
index register
C45016 for X and Y
Slide 15
Offset instruction illustration for
register X
Address
C000
Instruction
code
A6
C001
04
Mnemonic
Description
LDAA $04,X
Load
accumulator A
from address
[X]+04.
Effective Address = offset + [X]
= 04 + C450
= C454
Offset byte
Slide 16
Y register instruction illustration
Address
Instruction Mnemonic
code
Description
C000
18
Load
accumulator A
C001
LDAA $04,Y
A6
from address
[Y]+04.
04
Offset byte
Effective Address = offset + [Y]
= 04 + C450
= C454
Slide 17
Important process during the
operation
Accumulator A and B are cleared to zero before any ADD
operation occurs
Index register [X] is initially loaded with the number
2067
Accumulator B is initially loaded with 07 which the
number of memory locations to be added. ACCB is
being used to count down the number of times that
blocks 5-8 are executed
Blocks 5-8 are executed a total of seven times before
ACCB is decrement to 00 program goes to block 9 to
store the final sum in memory location 2068
The ADD operation (block 5) are executed using data
from different address each time starting with 2067 and
ending with 2061.this means the data is now loaded to
the accumulator
Slide 18
Start
1
Clear [ACCA]
2 Clear [ACCB]
3
Load [X] with Value 2067
4
Load [ACCB] with value 07
5
Add data stored at
address [X] +00 to [ACAA]
6
7
Decrement [X]
Decrement ACCB
8
No
Is [ACCB]=0?
9
Store [ACCA] in
memory
location 2068
10
HALT
Slide 19
Condition Code register
Consist of individual bits
Each bits is called Flags
This is the 68HC11code register
b7
b6
b5
b4
b3
b2
b1
b0
S
X
H
I
N
Z
V
C
Slide 20
Condition Code functions
C – Carry flag reflects the carry status of arithmetic
operation.
V – the overflow use to indicate overflow whenever
signed numbers are being added or subtracted
Z – zero flag is automatically set to 1
N – negative used to indicate any sign result of any
arithmetic data manipulation
I- interrupt mask flag is used to indicate effects on the
IRQ
H – Half carry flag is change only by addition instruction
X – X interrupt mask used to indicate not XIRQ
S – stop disable flag is used to prevent the stop
instruction
Slide 21
Conditional branching
It examine the value of the zero flag
If zero flag is = 0
The next instruction will be taken at a normal
sequence
If zero flag is = 1
The program will branch into new address for
the next instruction
If carry clear (BCC) or set booth will examine
the carry flag
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Two operands operators
Add
Subtract
Slide 28
Accumulator and memory
instructions
Slide 29
Load, Store and transfer instruction
Slide 30
Arithmetic operation instruction
Slide 31
Continuation..
Slide 32
Multiply and divide instruction
Slide 33
Logical operation instruction
Slide 34
Shift and rotate instructions
Slide 35
Stack and
index
register
instruction
Slide 36
Condition code register instruction
Slide 37
Slide 38
Branch
instructions
Slide 39