Chapter 6 Multi-channel Buffered Serial Port (McBSP) Objectives Definition of Terms: Bit, word or channel, frame and phase. Understand basic serial port operation. Understand clock generation. Pin.
Download ReportTranscript Chapter 6 Multi-channel Buffered Serial Port (McBSP) Objectives Definition of Terms: Bit, word or channel, frame and phase. Understand basic serial port operation. Understand clock generation. Pin.
Chapter 6
Multi-channel Buffered Serial Port
(McBSP)
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 2
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Basic Definitions: Bits, Words ?
CLK
FS
Data
Data a1 a0
b7 b6 b5 b4 b3 b2 b1 b0
Word
Bit
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 3
“Bit” - one data bit per SP clock period.
“Word” or “channel” contains #bits specified by
WDLEN1 (8, 12, 16, 20, 24, 32).
7
5
7
5
RWDLEN1
XWDLEN1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Basic Definitions: Frame?
FS
Data w6 w7
w0 w1 w2 w3 w4 w5 w6 w7
Frame
Word
“Frame” - contains one or multiple words
FRLEN1 specifies #words per frame (1-128)
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 4
14
8
7
5
RFRLEN1 RWDLEN1
14
8
7
5
XFRLEN1 XWDLEN1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Basic Definitions - Phase
FS
Data
1
Note: dual-phase
used in Audio
Codec97 (AC97) Std
2
3
A
Phase 1
B
Phase 2
Frame
Each FRAME can contain only 1 or 2 PHASES (PHASE).
Each PHASE can contain different #bits (WDLEN1/2) and #words
(FRLEN1/2) .
Phase 2
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 5
31
PHASE
31
PHASE
30
24
23
Phase 1
21
RFRLEN2 RWDLEN2
30
24
23
21
XFRLEN2 XWDLEN2
14
8
7
5
RFRLEN1 RWDLEN1
14
8
7
5
XFRLEN1 XWDLEN1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Basic Definitions - Phase
FS
8
Data
16
1
2
3
A
Phase 1
B
Phase 2
Frame
Each FRAME can contain 1 or 2 PHASES (PHASE).
Each PHASE can contain different #bits (WDLEN1/2) and #words
(FRLEN1/2) .
From above example some of the bit fields of RCR and XCR can
be initialised as shown below.
Phase 2
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 6
Phase 1
31
PHASE
30
24
RFRLEN2
23
21
RWDLEN2
8
14
RFRLEN1
7
5
RWDLEN1
31
PHASE
30
24
XFRLEN2
23
21
XWDLEN2
8
14
XFRLEN1
7
5
XWDLEN1
1
1
0001
0001
010
010
0010
0010
000
000
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Definitions - Review
CLK
b1 b2
Word 1
Word 2
Phase 1
Phase 2
Word 3
FS
Phase 1
Frame 1
Phase 2
Frame 2
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 8
31
PHASE
31
PHASE
30
24
23
21
RFRLEN2 RWDLEN2
30
24
23
21
XFRLEN2 XWDLEN2
14
8
7
5
RFRLEN1 RWDLEN1
14
8
7
5
XFRLEN1 XWDLEN1
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 9
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Block Diagram (Read)
RINT
DR
RSR
R
B
32 R
CPU
D
R
R
P
e
r
i
p
h
e
r
a
l
CLKR
B
u
s
FSR
Chapter 6, Slide 10
REVT
DMA
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Block Diagram (Write)
RINT
XINT
DR
DX
RSR
XSR
R
B
32 R
CPU
D
R
R
P
e
r
i
p
h
e
r
a
l
D
X
R
CLKR
CLKX
FSR
FSX
Chapter 6, Slide 11
B
u
s
REVT
XEVT
DMA
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Block Diagram (Configuration)
Multi-Channel Buffered
Serial Port (McBSP)
DR
RSR
DX
XSR
CLKR
CLKX
FSR
FSX
DRR
RBR
DXR
Serial Port
Control Logic
SPCR
RCR
?
XCR
?
CPU
P
e
r
i
p
h
B
u
s
DMA
Peripheral Bus
Chapter 6, Slide 12
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Serial Port - Basic Operation
Multi-Channel Buffered
Serial Port (McBSP)
DR
RSR
DX
XSR
CLKR
CLKX
FSR
FSX
DRR
RBR
DXR
Serial Port
Control Logic
SPCR
RCR
SRGR
XCR
PCR
Peripheral Bus
Chapter 6, Slide 13
CPU
P
e
r
i
p
h
B
u
s
DMA
“TRANSMIT”
“RECEIVE”
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Registers (1)
Receive
RSR
RBR
DRR
Receive Shift Reg
Receive Buffer Reg
Data Receive Reg
Transmit
XSR
DXR
Transmit Shift Reg
Data Transmit Reg
Control
SPCR
RCR
XCR
Serial Port Control Reg
Receive Control Reg
Transmit Control Reg
Chapter 6, Slide 14
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 15
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Configure CLK and FS as inputs or outputs
Multi-Channel Buffered
Serial Port (McBSP)
CLKR
CLKX
FSR
FSX
Chapter 6, Slide 16
Serial Port
Control Logic
SPCR
RCR
SRGR
XCR
PCR
FSR, FSX, CLKR and CLKX can be configured
either as inputs or outputs, depending on the
application.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Configure CLK and FS as inputs or outputs
Multi-Channel Buffered
Serial Port (McBSP)
CLKR
CLKX
FSR
FSX
Serial Port
Control Logic
SPCR
RCR
SRGR
XCR
PCR
CLK/FS Mode
0: Input
1: Output
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 17
11
10
9
8
FSXM
FSRM
CLKXM
CLKRM
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Generating CLK and FS as output
‘C6000
FSR
FSX
CLKR
CLKX
CLK/FS Mode
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 18
0: Input
1: Output
11
10
9
8
FSXM
FSRM
CLKXM
CLKRM
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Generating the CLK as output
‘C6000
Sample Rate Generator (SRGR)
CLKOUT1
FSR
FSX
CLKS
CLKGDV
CLKG
CLKR
CLKX
CLKSM
CLKSM - selects clock src (CLKOUT1 or CLKS)
CLKGDV - divide down (1-255)
CLKG = (input clock) / (1 + CLKGDV)
Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/s
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 19
29
CLKSM
7
0
CLKGDV
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Generating the FS as output
‘C6000
Sample Rate Generator (SRGR)
CLKOUT1
CLKS
FSG
FSR
FSX
CLKG
CLKR
CLKX
FPER
CLKGDV
CLKSM
FSGM: 0 - FS gen’d on every DXR XSR copy
1 - FS gen’d by FSG
Serial Port
FPER:
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
FWID: frame sync pulse width (8 bits)
Chapter 6, Slide 20
29
frame sync period (12 bits)
28
CLKSM FSGM
27
16
FPER
15
FWID
8
7
0
CLKGDV
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Registers (2)
Receive
RSR
RBR
DRR
Receive Shift Reg
Receive Buffer Reg
Data Receive Reg
Transmit
XSR
DXR
Transmit Shift Reg
Data Transmit Reg
SPCR
RCR
XCR
SRGR
Serial Port Control Reg
Receive Control Reg
Transmit Control Reg
Sample Rate Generator
Control
Chapter 6, Slide 21
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 22
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Configure CLK and FS pin polarity
Multi-Channel Buffered
Serial Port (McBSP)
CLKR
CLKX
FSR
FSX
Serial Port
Control Logic
SPCR
RCR
SRGR
XCR
PCR
CLK/FS Polarity
0: Falling edge
1: Rising Edge
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 23
3
2
1
0
FSXP
FSRP
CLKXP
CLKRP
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 24
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
RRDY/XRDY Status and Interrupts
RBR
DRR
RRDY=1
“Ready to Read”
XSR
DXR
XRDY=1
“Ready to Write”
CPU
RRDY/XRDY displays the
“status” of the read and
transmit ports:
0: not ready.
1: ready to read/write.
There are 3 methods for
detecting if data is ready:
RINT
XINT
EDMA
Sync
Poll SPCR bits via s/w.
Config CPU ints
(RINT/XINT).
Program DMA sync events.
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 25
17
1
XRDY
RRDY
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Other sources of Interrupts (R/XINT)
“Trigger Event”
RRDY
End of Block (RCV)
New FSR (frame begin)
Receive Sync Error
(RINTM=00b)
(RINTM=01)
(RINTM=10b)
(RINTM=11b)
RINT
XRDY
End of Block (XMT)
New FSX (frame begin)
Transmit Sync Error
(XINTM=00b)
(XINTM=01b)
(XINTM=10b)
(XINTM=11b)
XINT
CPU
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Chapter 6, Slide 26
21
20
XINTM
17
XRDY
5
4
RINTM
1
RRDY
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 27
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Multi-Channel operation
DR/X
Ch0
Ch1
...
Ch31 Ch0
Ch1
...
Ch31
FSR/X
How do you enable/disable each channel?
Chapter 6, Slide 28
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Multi-Channel operation
DR/X
Ch0
Ch1
...
Ch31 Ch0
Ch1
...
Ch31
FSR/X
You can enable or disable any channel.
RCER/XCER Enable Bits
Enable
[1]
Disable [0]
Multi-Channel
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Chapter 6, Slide 29
31
0
0
RCER
31
… 1110
0
XCER
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Multi-channel example
F
r
a
m
e
r
Frame 3
4
3
2
Frame 2
1
4
3
2
Frame 1
1
4
3
2
1
Memory
Allows multiple channels (words) to
be independently selected for
transmit and receive.
Chapter 6, Slide 30
M
c
B
S
P
1
3
1
3
..
.
1
3
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Multi-channel and EDMA combination used
for channel sorting
F
r
a
m
e
r
Frame 3
4
3
2
Frame 2
1
4
3
2
Frame 1
1
4
3
2
1
Memory
M
c
B
S
P
EDMA’s can sort each channel
into separate buffers!
Chapter 6, Slide 31
E
D
M
A
1
1
1
..
.
3
3
3
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
EDMA Channel Sorting
F
r
a
m
e
r
Frame 3
4
3
2
Frame 2
1
4
3
2
Frame 1
1
4
3
2
1
Memory
M
c
B
S
P
EDMA’s flexible (indexed) addressing allows
it to sort each channel into separate buffers!
How do you select channels? ...
Chapter 6, Slide 32
E
D
M
A
1
1
1
..
.
3
3
3
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Enable/Disable Channels
RCER / XCER registers allow you to enable or
disable only 32-channels.
So how does the C6000 supports 128 channels?
Multi-Channel
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Chapter 6, Slide 33
31
0
RCER
31
… 1010
0
XCER
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
128 Channels!
Channels
0-15
16-31
32-47
48-63
64-79
80-95
96-111 112-127
A
B
Interrupt
To be able to support 128 channels the following applies:
Channels are broken into BLOCK’s (16 contiguous channels).
Up to 32 channels (2 BLOCK’s) can be enabled at any one time.
Channels are enabled via _CER registers and _BLK bits in MCR.
After 16 channels, McBSP issues END_OF_BLOCK interrupt.
CPU ISR re-programs RCER (or XCER) for channels 32-47 and so
on.
Multi-Channel
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Chapter 6, Slide 34
31
16 15
B15-0
31
RCER
0
A15-0
16 15
B15-0
XCER
0
A15-0
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
McBSP Registers (3)
Receive
RSR
RBR
DRR
Receive Shift Reg
Receive Buffer Reg
Data Receive Reg
Transmit
XSR
DXR
Transmit Shift Reg
Data Transmit Reg
SPCR
RCR
XCR
SRGR
PCR
MCR
RCER
XCER
Serial Port Control Reg
Receive Control Reg
Transmit Control Reg
Sample Rate Generator
Pin Control Reg
Multi-Channel Ctrl Reg
Rcv Channel Enable Reg
Xmit Channel Enable Reg
Control
Chapter 6, Slide 35
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Objectives
Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.
Chapter 6, Slide 36
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port
There are three methods available for
programming the serial port:
1. Writing directly to the serial port registers.
2. Using the Chip Support Library (CSL).
3. Graphically using the DSP/BIOS GUI
configuration tool.
Chapter 6, Slide 37
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - Direct
(A) Writing directly to the serial port
registers:
Although this method is straight forward, it relies
on a good understanding of the serial port
functionality.
This method can be tedious and is prone to errors.
#include <c6211dsk.h>
void mcbsp0_init()
{
*(unsigned volatile
*(unsigned volatile
*(unsigned volatile
*(unsigned volatile
*(unsigned volatile
*(unsigned volatile
}
Chapter 6, Slide 38
int
int
int
int
int
int
*)McBSP0_SPCR = 0;
*)McBSP0_PCR = 0;
*)McBSP0_RCR = 0x10040;
*)McBSP0_XCR = 0x10040;
*)McBSP0_DXR = 0;
*)McBSP0_SPCR = 0x12001;
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (1/4)
(B) Using the Chip Support Library:
Chapter 6, Slide 39
The CSL provides a C language interface
for configuring and controlling the on-chip
peripherals, in this case the Serial Ports.
The library is modular with each module
corresponding to a specific peripheral.
This has the advantage of reducing the
code size.
Some modules rely on other modules also
being included, for example the IRQ
module is required when using the EDMA
module.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (1/4)
CSL programming procedure:
(1) Create handles for the serial ports:
MCBSP_Handle hMcbsp;
(2) Open the serial port:
hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
Chapter 6, Slide 40
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (2/4)
CSL programming procedure:
(3) Create a configuration structure for serial
port:
Chapter 6, Slide 41
\Links\McBSP_Config_Struct.pdf
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (3/4)
CSL programming procedure (cont):
(4) Configure the serial port:
MCBSP_config(hMcbsp,&ConfigLoopback);
(5) Close the Serial Port after use:
MCBSP_close(hMcbsp);
Chapter 6, Slide 42
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (4/4)
Practical example on DSP Code 6711
Project name: mcbsp_dynamiccfg.pjt
Location: \Code\Chapter 06 - McBSP\Dynamic_CSL_Config\
Chapter 6, Slide 43
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
(C)
DSP/BIOS GUI Interface:
Chapter 6, Slide 44
With this method the configuration structure
is created graphically and the setup code is
generated automatically.
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Procedure:
(1) Create a configuration using the
MCBSP Configuration manager (eg.
mcbspCfg0).
Chapter 6, Slide 45
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Procedure:
(2) Right click on mcbspCfg0 and select
“Properties”, see figures below, and then
select “Advanced” and fill all parameters
as shown below:
Chapter 6, Slide 46
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Procedure:
(3) Select the serial port you would like to use
from the MCBSP Resource manager (eg.
Mcbsp_Port1).
Right click and select properties.
Select the mcbspCfg0 configuration just created.
Chapter 6, Slide 47
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Procedure:
(4) A file is then generated that contains the
configuration code. The file generated for
this example is shown on the next slide.
Chapter 6, Slide 48
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
/*
/*
/*
Do *not* directly modify this file. It was
generated by the Configuration Tool; any */
changes risk being overwritten.
*/
*/
/* INPUT mcbsp1.cdb */
/* Include Header File
#include "mcbsp1cfg.h"
*/
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x00008000,
/*
0x000000A0,
/*
0x000000A0,
/*
0x203F1F0F,
/*
0x00000000,
/*
0x00000000,
/*
0x00000000,
/*
0x00000A00
/*
};
Serial Port Control Reg. (SPCR)
*/
Receiver Control Reg. (RCR)
*/
Transmitter Control Reg. (XCR)
*/
Sample-Rate Generator Reg. (SRGR)
*/
Multichannel Control Reg. (MCR)
*/
Receiver Channel Enable(RCER)
*/
Transmitter Channel Enable(XCER)
*/
Pin Control Reg. (PCR)
*/
/* Handles */
MCBSP_Handle hMcbsp1;
/*
* ======== CSL_cfgInit() ========
*/
void CSL_cfgInit()
{
hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp1, &mcbspCfg0);
}
Chapter 6, Slide 49
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Few remarks:
(1) Notice that values in the code generated are the
same as the values inserted using the GUI interface.
/*
Do *not* directly modify this file. It was
*/
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x00008000,
/* Serial Port Control Reg. (SPCR)
*/
0x000000A0,
/* Receiver Control Reg. (RCR)
*/
0x000000A0,
/* Transmitter Control Reg. (XCR)
*/
0x203F1F0F,
/* Sample-Rate Generator Reg. (SRGR)
*/
0x00000000,
/* Multichannel Control Reg. (MCR)
*/
0x00000000,
/* Receiver Channel Enable(RCER)
*/
0x00000000,
/* Transmitter Channel Enable(XCER)
*/
0x00000A00
/* Pin Control Reg. (PCR)
*/
};
Chapter 6, Slide 50
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port using the
DSP/BIOS GUI
Few remarks:
(2) Do not forget to close the serial port after use.
(3) To visualise the output
of the logprintf ()
function make sure
that the Message Log
window is open
(DSP/BIOS > Message
Log).
Chapter 6, Slide 51
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Programming the Serial Port - CSL (4/4)
Practical example
Chapter 6, Slide 52
Project name: mcbsp_staticcfg.pjt
Location: \Code\Chapter 06 - McBSP\Static_CSL_Config\
Extra Topic: Digital Loopback
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 6
Multi-channel Buffered Serial Port
(McBSP)
- End -