Transcript Clock divider and review of course DSD Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock.

Clock divider and
review of course
DSD
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock
1
Using counter for clock division
The outputs q[i] of a counter are square waves where the output q[0] has a
frequency half of the clock frequency, the output q[1] has a frequency half of
q[0], etc. Thus, a counter can be used to divide the frequency f of a clock,
where the frequency of the output q(i) is f(i)= f/2^i+1.
The frequencies and periods of the outputs of a 24-bit counter driven by a 50
MHz clock are shown in Table 1. Note in Table 1 that the output q[0] has a
frequency of 25 MHz, the output q[17] has a frequency of 190.73 Hz, and the
output q[23] has a frequency of 2.98 Hz.
Table 1
Clock divider and
review of course
module clkdiv (
input clk ,
input clr ,
output clk190 ,
output clk25 ,
output clk3
);
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock
4
reg [23:0] q;
// 24-bit counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
q <= 0;
else
q <= q + 1;
end
assign clk190 = q[17]; // 190 Hz
assign clk25 = q[0]; // 25 MHz
assign clk3 = q[23]; // 3 Hz
endmodule