Transcript PicoBlaze CPLD Microcontroller Agenda • • • • • • What is PicoBlaze PicoBlaze operation PicoBlaze software flow Customize PicoBlaze Memory integration Why PicoBlaze Quick Start Training.

PicoBlaze CPLD
Microcontroller
Agenda
•
•
•
•
•
•
What is PicoBlaze
PicoBlaze operation
PicoBlaze software flow
Customize PicoBlaze
Memory integration
Why PicoBlaze
Quick Start Training
What is PicoBlaze?
• A fully customizable 8-bit soft microcontroller
macros that provides
–
–
–
–
49 16-bit instructions
8 general-purpose 8-bit registers
256 directly and indirectly addressable ports
Reset and a maskable interrupt
Quick Start Training
PicoBlaze Block Diagram
8
8
8
8
8 Registers 8-bit
IN_PORT
Interrupt
Control
INSTRUCTION
16
RESET
CLK
Quick Start Training
Operational
Control &
Instruction
Decoding
8
CONSTANT DATA
8
PORT_ID
READ_STROBE
WRITE_STROBE
OUT_PORT
8
8
INTERRUPT
8
Port
Address
Control
8
ALU
Interrupt
Flag
Store
ZERO &
CARRY
Flags
Program
Flow
Control
8
Program
Counter
8
Program
Counter
Stack
8
ADDRESS
PicoBlaze Operation
PicoBlaze
IN_PORT[7:0]
OUT_PORT[7:0]
PORT_ID[7:0]
READ_STROBE
INTERRUPT
Program ROM
RESET
INSTRUCTION[15:0]
INSTRUCTIOIN[15:0]
ADDRESS[7:0]
WRITE_STROBE
ADDRESS[7:0]
CLK
CLK
2 clock cycle operation
CLK
RESET
ADDRESS(7:0)
INSTRUCTION(15:0)
Quick Start Training
00
00
0700
01
0700
02
0801
03
F632
04
DC5A
PicoBlaze Instruction Set
• Program Control
Group
– JUMP
– CALL
– RETURN
• Logical Group
–
–
–
–
LOAD
AND
OR
XOR
• Arithmetic Group
–
–
–
–
ADD
ADDCY
SUB
SUBCY
Quick Start Training
• Shift & Rotate Group
–
–
–
–
–
–
–
–
–
–
SR0
SR1
SRX
SRA
RR
SL0
SL1
SLX
SLA
RL
• Input/Output Group
– INPUT
– OUTPUT
• Interrupt Group
–
–
–
–
RETURNI ENABLE
RETURNI DISABLE
INTERRUPT ENABLE
INTERRUPT DISABLE
Assembler
•
•
•
•
A simple DOS executable file
Written in C
Use Microsoft Visual Studio 6.0
Easy to change
Quick Start Training
Assembler Files
Filename.asm
<User input file>
ASM.EXE
<Binary code for ROM>
Quick Start Training
Filename.mcs
Filename.vhd <VHDL for simulation>
Filename.bin
<Binary code in hex format>
Filename.fmt
<Formatted assembly file>
Filename.log
<Assembler report>
A Simple Shifter
Constant shifter_port, 04
;declare port
Namereg s7, shifter_reg
;declare register
Loop1: Load shifter_reg, 01
;init shifter reg
Loop2: Output shifter_reg, shifter_port
Quick Start Training
SL0 shifter_reg
;shift left with 0
Jump NZ, loop2
;goto loop2 when s7<>0
Jump loop1
;goto loop1
Shifter Program
Address
Hex
Binary
00
0701
0000011100000001
Load s7, 01
01
8F04
1000111100000100
Output s7, 04
02
A706
1010011100000110
SL0 s7
03
D501
1101010100000001
Jump NZ, 01
04
D000
1101000000000000
Jump 00
Quick Start Training
PicoBlaze Software Flow
• Compile PicoBlaze source
– Use WebPACK 5.2i or later
– Use FISE 5.2i or later
• Assemble the program code
– asm filename.asm
• Download to the CPLD
– iMPACT 5.2i or later
• Download assembled object code to EEPROM
Quick Start Training
Making a Processor Change
• Add an instruction
– Modify picoblaze.vhd
– Add a constant with instruction code:
constant new_instruction_id : std_logic_vector(4 downto 0) := “10101";
– Add instruction decoding signal
i_new_instruction <= '1' when instruction(15 downto 11) = new_instruction_id
else '0';
– Define VHDL component with functionality of new instruction
– Add new component to picoblaze.vhd
• Tweak the assembler
– Add new instruction to asm.cpp
char *new_instruction_id = “10101“;
– Add case to write_program_word function of asm.cpp
– Recompile asm.cpp to create asm.exe
Quick Start Training
Making a Processor Change
• A DSP example - bit reversal (“Flip”) operation
A
B
C
D
E
F
G
H
H
G
F
E
D
C
B
A
• 12 to 18 instructions needed in regular microcontroller
programming
• A newly created FLIP function in PicoBlaze can be used
to complete the operation in just one instruction cycle
Quick Start Training
Macrocell Usage
Quick Start Training
Program Memory Integration
• Binary code and processor can be integrated into
a single CPLD
• Eliminates external PROM
• SOC solution
• Reduces size
• Increases performance
Quick Start Training
Integration Design Flow
• Assemble the design
– Use PicoBlaze Assembler
– asm design.asm
– Generates design.vhd
• Write top level VHDL
– Wrap picoblaze.vhd and design.vhd (output from assembler)
• Compile top level VHDL source
– Use WebPACK 5.2i or later
– Use FISE 5.2i or later
• Download to CPLD
– Use iMPACT 5.2i or later
Quick Start Training
1+1<2
PicoBlaze
Macrocells
Product Terms
Registers
FB Inputs
Fmax
212/256 ( 83%)
642 /896 ( 72%)
155/256 ( 61%)
451/640 ( 70%)
30 MHz
PicoBlaze + Shifter
Macrocells
Product Terms
Registers
FB Inputs
Fmax
107/256 ( 42%)
341 /896 ( 38%)
82 /256 ( 32%)
208/640 ( 32%)
87 MHz
- Fitter removes redundant circuits
Quick Start Training
PicoBlaze Demonstration
• Demonstrate simple shifter
• Add FLIP instruction
– Exchanges bits in specified register
• MSB to LSB
• LSB to MSB
– Modify picoblaze.vhd
– Create FLIP component
– Modify asm.cpp
• Demonstrate FLIP instruction with new program
Quick Start Training
Why Use PicoBlaze?
• Emulate out of production processors
• Lower power consumption than older small processors
• Customizable for performance
– PicoBlaze runs faster than most 8-bit and16-bit uCs (PICs,
8051, 6811, 80188, 6816, etc.)
• Customizable for specific applications
– uCs have fixed features
– uCs have fixed instructions sets
– PicoBlaze can run functions quickly in parallel logic
Quick Start Training
Why Use PicoBlaze?
• PicoBlaze is parameterized
– uCs have fixed size
– uCs have limited I/Os
• Can be reconfigured “On the Fly (OTF)”
• Cryptography/security
Quick Start Training
Conclusion
• PicoBlaze is a soft microcontroller module
• Use PicoBlaze for custom microcontroller
applications
• Create custom instruction sets
• Program memory integration
• Use PicoBlaze Assembler
• Compile with current Xilinx software
Quick Start Training
CoolRunner-II Reference Designs
PDA
Datacom
Encoder
Decoder
Memory
Wirless
Consumer
Lanaguage
Macrocell
XPATH Module Design
8 Channel DVM Springboard
Springboard Module Design
8051 Microcontroller Interface
SPI
IrDA and UART
UARTS
Reference
Number
XAPP356
XAPP146
XAPP147
XAPP349
XAPP348
XAPP345
XAPP341
VHDL
Pocket C, VHDL
Pocket C, VHDL
VHDL
VHDL
VHDL or Verilog
VHDL or Verilog
I2C Bus Controller
XAPP333
XAPP380
XAPP353
XAPP339
XAPP336
XAPP383
XAPP354
XAPP358
XAPP328
Reference Design
Application
N x N Crosspoint Switch
SMBus Controller
Manchester Encoder/Decoder
16b/20b Encoder/Decoder
Error Detection & Correction
NAND Interface
Wireless Transciever
MP3 Player
225
184
67
57
135
87
61
Target
Device
XC2C384
XC2C256
XC2C128
XC2C64
XC2C256
XC2C128
XC2C128
%
Utilizated
58
71
52
89
52
67
47
VHDL or Verilog
131
XC2C256
51
VHDL
VHDL
VHDL or Verilog
VHDL
VHDL
VHDL or Verilog
VHDL
VHDL
193
158
55
76
66
9
156
225
XC2C256
XC2C256
XC2C64
XC2C128
XC2C128
XC2C32
XC2C256
XC2C256
75
61
85
59
52
28
60
88
Free HDL CoolRunner-II design code download:
http://www.xilinx.com/products/xaw/coolvhdlq.htm
Quick Start Training
Appendix A
• Instruction set descriptions
– Syntax
– Bit description
Quick Start Training
Program Syntax
• No blank lines – Use a semicolon for blank lines
• Comments – Any item on a line following a semicolon (;)
• Constant – Must be specified in the form of a 2 digit hexadecimal
value(00 – FF)
• Line Labels – To identify a program line for JUMP or CALL instruction
should be followed by a colon (:)
• CONSTANT Directive – Assigns an 8-bit constant value to a label
• NAMEREG Directive – Assigns a new name to any of the 8 registers
• ADDRESS Directive – Forces the following instructions commencing at a
new address value
Quick Start Training
Program Control
JUMP aa
1 1 0 1 0 JUMP
1 1 0 1 1 CALL
JUMP Z, aa
1 0 0 1 0 RETURN
JUMP NC, aa
JUMP NZ, aa
JUMP C, aa
Address
CALL aa
CALL Z, aa
I I I I I C C C A A A A A A A A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CALL NZ, aa
CALL C, aa
CALL NC, aa
Unconditional
Conditional
0 0 0 if Zero
1 0 1 if NOT Zero
1 0 if Carry
1 1
Quick Start Training
if NOT Carry
RETURN
RETURN Z
RETURN NZ
RETURN C
RETURN NC
Instruction syntax
Interrupt Control
Instruction syntax
INTERRUPT ENABLE
INTERRUPT DISABLE
1 1 1 1 0
INTERRUPT
ENABLE INTERRUPT
1 0 1 1 0
RETURNI
DISABLE INTERRUPT
Don’t Care
I I I I I 0 0 0 0 0 0 0 0 0 0 C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Enable
Disable
Quick Start Training
0
0
1
Logical Operation
0
0
0
0
C
C
C
C
0
0
0
0
0
0
1
1
LOAD sX, KK
LOAD sX, C
0
1
0
1
AND sX, KK
AND sX, C
OR sX, KK
OR sX, C
XOR sX, KK
XOR sX, C
LOAD sX, sY
Constant
AND sX, sY
OR sX, sY
I I I I I X X X Y Y Y K K K K K
15
14
13
12
0
K
1
sY
Quick Start Training
11
10
9
sX
8
7
6
sY
5
4
3
2
1
0
XOR sX, sY
Instruction syntax
Arithmetic Operation
ADD sX, KK
0 C 1 0 0
0 C 1 0 1
ADD sX, C
ADDCY sX, C
SUB sX, KK
0 C 1 1 0
0 C 1 1 1
SUB sX, C
SUBCY sX, KK
ADDCY sX, KK
ADD sX, sY
SUBCY sX, C
Constant
ADDCY sX, sY
I I I I I X X X Y Y Y K K K K K
15
14
0
1
Quick Start Training
13
12
K
sY
11
10
9
sX
8
7
6
sY
5
4
3
2
1
0
SUB sX, sY
SUBCY sX, sY
Instruction syntax
SHIFT/ROTATE
1
0
1
0
1
0
1
0
SR0/SL0
1 1 0
SR1/SL1
1
0
0
1
SRX/SLX
1
0
1
0
1
0
1
0
SRA/SLA
Carry
Instruction
RR/RL
1
1
0
0
1
0
0
0
1 0 1 0 0 X X X 0 0 0 0 C D D D
15
14
13
12
11
10
9
sX
Quick Start Training
8
7
6
5
4
3
0
1
2
1
0
L - Left
R - Right
SR0 sX
SR1 sX
SRX sX
SRA sX
RR sX
SL0 sX
SL1 sX
SLX sX
SLA sX
RL sX
Instruction syntax
Input/Output Control
INPUT sX, PP
INPUT sX, sY
1 C 0 0 0
Input
OUTPUT sX, PP
1 C 0 0 1
Output
OUTPUT sX, sY
Constant PORT_ID
Instruction syntax
I I I I I X X X Y Y Y P P P P P
15
14
13
0
1
Quick Start Training
12
P
sY
11
10
9
sX
8
7
6
sY
5
4
3
2
1
0