Transcript Few important advantages of FET over conventional Transistors 1. 2. Unipolar device i.

Few important advantages of FET over conventional Transistors
1.
2.
Unipolar device i. e. operation depends on only one type of
charge carriers (h or e)
Voltage controlled Device (gate voltage controls drain
current)
3.
Very high input impedance (109-1012 )
4.
Source and drain are interchangeable in most Low-frequency
applications
5.
Low Voltage Low Current Operation is possible (Low-power
consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Very small in size, occupies very small space in ICs
Low voltage low current operation is possible in MOSFETS
Zero temperature drift is possible
6.
7.
8.
9.
10.
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
FET
JFET
MOSFET (IGFET)
Enhancement
MOSFET
n-Channel
EMOSFET
p-Channel
EMOSFET
n-Channel JFET
p-Channel JFET
Depletion
MOSFET
n-Channel
DMOSFET
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p-Channel
DMOSFET
October, 16
The Junction Field Effect Transistor (JFET)
Figure: n-Channel JFET.
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SYMBOLS
Drain
Drain
Drain
Gate
Gate
Gate
Source
n-channel JFET
Source
n-channel JFET
Offset-gate symbol
Source
p-channel JFET
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Biasing the JFET
Figure: n-Channel JFET and Biasing Circuit.
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Operation of JFET at Various Gate Bias Potentials
Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)
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Operation of a JFET
Drain
-
N
Gate
+
P
P
N
+
+
-
Source
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Output or Drain (VD-ID) Characteristics of n-JFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Non-saturation (Ohmic) Region:
The drain current is given by
V
I
DS
Saturation (or Pinchoff) Region:
I
DS

I
DSS
V2
P

V
V
GS
P




2I
DSS
V2
P

V 
V

DS
P 
 GS

V2


 V V
 DS
V
 GS
P  DS
2


V
2

 
 

 V
 V 
DS
P
 GS

V

GS
and I
I
1

DS
DSS 
V

P






2





Where, IDSS is the short circuit drain current, VP is the pinch off voltage
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Simple Operation and Break down of n-Channel JFET
Figure: n-Channel FET for vGS = 0.
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N-Channel JFET Characteristics and Breakdown
Break Down Region
Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.
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VD-ID Characteristics of EMOS FET
Locus of pts where VDS  VGS  VP 
Saturation or Pinch
off Reg.
Figure: Typical drain characteristics of an n-channel JFET.
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Transfer (Mutual) Characteristics of n-Channel JFET

V

GS
I
I
1

DS
DSS 
V

P

2




IDSS
VGS (off)=VP
Figure: Transfer (or Mutual) Characteristics of n-Channel JFET
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


Fixed bias circuit
Self bias circuit
Potential Divider bias circuit
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For Fixed Bias Circuit
Applying KVL to gate circuit we get
VGG  I G RG  VGS  VGS  Fixed, I G  0
2
 V 
1  GS 
I I
DS
DSS 
V 
P 

and
2
 VGS 

I DS  I DSS 1 
VP 

and VDS  VDD  I DS RD
Where, Vp=VGS-off & IDSS is Short ckt. IDS
For Self Bias Circuit
VGS  I DS RS  0
 I DS  
VGS
RS
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VGG + IGRG + VGS = 0
Since IG = 0
VGS = - VGG
Since GS is
reverse biased, IG
= 0 and VRG = 0
RG is present to limit current
in case VGG is connected
with wrong polarity
This would forward bias the
gate-source junction causing
high currents, which would
destroy the transistor
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16
VGS 

ID = IDSS  1 
VP 

2
2
VGS = - VGG
 V 
I DS  I DSS 1  GS 
VP 

and VDS  VDD  I DS RD
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17
or Fixed Bias Ckt.
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DC Equivalent Circuit
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19
IG = 0
VGS  I DS RS  0
 I DS
VGS

RS
VRG = 0
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20
JFET Self (or Source) Bias Circuit
2

V

and I
I
1  GS

DS
DSS 
V
P







V

GS
I
1

DSS 
V

P

V
2




  GS
R
S

V
V

GS   GS
I
1

2
 V
DSS 
V

P
 P

2




 VGS
 R 0

S

This quadratic equation can be solved for VGS & IDS
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22
Input
 R2 
VG = VDD 

R
1
+
R
2


October, 16
Output
-VG + VGS + IDRS = 0
VGS = VG - IDRS
VDS = VDD - ID (RD + RS)
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The Potential (Voltage) Divider Bias

V

GS
I
1

DSS 
V

P

2






V
G
V
GS
R
0
S
Solving this quadratic equation gives V
GS
and I
DS
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A Simple CS Amplifier and Variation in IDS with Vgs
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FET Mid-frequency Analysis:
VDD
A common source (CS) amplifier is shown
to the right.
RD
R1
io
The mid-frequency circuit is drawn as follows:
• the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
• short the DC supply voltage (superposition)
• replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.
is
ii
+
vs
D
ii
Rs
+
vs
RTh
Ci
vi
S
RSS
io
+
gmvp
rd
RD
RL
vo
_
_
s
mid-frequency CE amplifier circuit
Analysis of the CS mid-frequency circuit above yields:
A vi =
vo
= -g m R 'L , where R 'L = rd R D R L
vi
A vs =
Zi =
vi
= R Th , where R Th = R1 R 2
ii
AI =
Zo =
vo
io
AP =
= rd R D
seen by R L
 Zi

vo
= A vi 

vs
 R s + Zi 
io
= A vi
ii
vo
R2
_
d
vi = vp
s
+
+
_
g
Co
G
RL
+
_
VDD
 Zi 


 RL 
po
= A vi A I
pi
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CSS
_
FET Mid-frequency Analysis:
VDD
A common source (CS) amplifier is shown
to the right.
RD
R1
io
D
ii
The mid-frequency circuit is drawn as follows:
• the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
• short the DC supply voltage (superposition)
• replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.
is
ii
+
vs
_
Ci
S
RL
vs
vi
RSS
_
io
+
gmvp
rd
RD
RL
vo
_
_
s
mid-frequency CE amplifier circuit
Analysis of the CS mid-frequency circuit above yields:
A vi =
vo
= -g m R 'L , where R 'L = rd R D R L
vi
A vs =
 Zi 
vo
= A vi 

vs
 R s + Zi 
Zi =
vi
= R Th , where R Th = R1 R 2
ii
AI =
Z 
io
= A vi  i 
ii
 RL 
Zo =
vo
io
AP =
po
= A vi A I
pi
= rd R D
seen by R L
vo
R2
_
d
vi = vp
s
+
+
g
Co
G
+
Rs
+
RTh
VDD
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CSS
_
Procedure: Analysis of an FET amplifier at mid-frequency:
1) Find the DC Q-point. This will insure that the FET is operating in the saturation
region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
gm =
2I
ID
= DSS
 VGS - VP 
VGS
VP2
gm =
ID
= K  VGS - VT 
VGS
(for JFET's and DM MOSFET's)
(for EM MOSFET's)
(Note: Uses DC value of VGS )
3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).
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PE-Electrical Review Course - Class 4 (Transistors)
18 V
Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi,
and Zo for the amplifier shown below. Assume that
Ci, Co, and CSS are large.
Note that this is the same biasing circuit used in Ex. 2,
so VGS = -0.178 V.
The JFET has the following specifications:
IDSS = 4 mA, VP = -1.46 V, rd = 50 k
18 V
500
800 k
io
D
ii
10 k
+
vs
Co
G
+
+
Ci
S
8k
vi
vo
400 k
_
2k
_
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CSS
_
VDD
FET Amplifier Configurations and
Relationships:
VDD
RD
R1
io
D
ii
CS
Co
G
+
Rs
+
+
Ci
S
RL
vs
vo
CSS
RSS
_
_
Common Source (CS) Amplifier
ii
D
S
+
-g m R
G
+
RD
RSS
RL
_
R1
_
R 'L
rd R D R L
Zi
R Th
Zo
rd R D
C2
vo
_
R2
VCC
A vs
Common Gate (CG) Amplifier
VDD
AI
VDD
R1
AP
D
ii
Rs
+
vs
gmR
rd R D R L
R SS
io
Ci
vi
A vi
'
L
1
gm
CD
g m R 'L
1  g m R 'L
R SS R L
R Th
Co
+
vs
'
L
R2
vi
_
Rs
CG
rd R D
R SS
1
gm
 Zi 
 Zi 
 Zi 
A vi 
A
A
vi 
vi 



R
+
Z
R
+
Z
R
+
Z
i 
i 
i 
 s
 s
 s
Z 
A vi  i 
 RL 
A vi A I
Z 
A vi  i 
 RL 
A vi A I
Z 
A vi  i 
 RL 
A vi A I
G
+
vi
_
S
Ci
where R Th = R1 R 2
io
Co
R2
R SS
_
+
RL
vo
_
Note: The biasing circuit is the same for each amp.
Common Drain (CD) Amplifier (also called “source follower”)
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Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.
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Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.
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Figure: For vGS < Vto the pn junction between drain and body is reverse biased and i D=0.
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Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate.
As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.
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Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly.
Finally for vDS> vGS -Vto, iD becomes constant.
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Locus of points where
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Figure: Drain characteristics
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Figure: This circuit can be used to plot drain characteristics.
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Figure: Diodes protect the oxide layer from destruction by static electric charge.
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Figure: Simple NMOS amplifier circuit and Characteristics with load line.
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Figure: Drain characteristics and load line
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Figure vDS versus time for the circuit of Figure 5.13.
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Figure Fixed- plus self-bias circuit.
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Figure Graphical solution of Equations (5.17) and (5.18).
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Figure Fixed- plus self-biased circuit of Example 5.3.
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Figure The more nearly horizontal bias line results in less change in the Q-point.
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Figure Small-signal equivalent circuit for FETs.
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Figure FET small-signal equivalent circuit that accounts for the dependence of iD on vDS.
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Figure Determination of gm and rd. See Example 5.5.
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Figure Common-source amplifier.
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For drawing an a c equivalent circuit of Amp.
•Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
•Short circuit the d c supply
•Replace the FET by its small signal model
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A C Equivalent Circuit
Simplified A C Equivalent Circuit
v
Voltage gain, A  o
v v
gs
v  i R  g v R
Out
Zm gsr LR 
o put
o imp.,
L
o
v
d
D
r R
d D
r R
d
Input imp., Z
in
R R R
G
D
 A  o  g R , R  R r
v v
m L
L
D d
gs
October, 16
1
2
Av  gm(rd || RD)
This is a CS amplifier configuration therefore the
input is on the gate and the output is on the drain.
Av  gm(rd || RD)
Av  gmRD,  r  10 R
d
Zi  R1 || R2
Zo rd || RD
Zo  RD
rd 10RD
D
October, 16
Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
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An Amplifier Circuit using MOSFET(CS Amp.)
Figure Common-source amplifier.
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A small signal equivalent circuit of CS Amp.
Figure Small-signal equivalent circuit for the common-source amplifier.
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Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
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Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.
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Figure Source follower.
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Figure Small-signal ac equivalent circuit for the source follower.
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Figure Equivalent circuit used to find the output resistance of the source follower.
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Figure Common-gate amplifier.
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Figure See Exercise 5.12.
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Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.
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Figure n-Channel depletion MOSFET.
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Figure Characteristic curves for an NMOS transistor.
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Figure Drain current versus vGS in the saturation region for n-channel devices.
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Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,
except for the directions of the arrowheads.
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Figure Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal
for n-channel devices and out of the drain for p-channel devices.
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